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Kodiak PCIe phy refclk always on changes #29

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d95fd32
FROMLIST: dt-bindings: phy: qcom,qmp: Add PCIe qcom,refclk-always-on …
Nov 27, 2023
66f5855
FROMLIST: phy: qcom-qmp-pcie: Add endpoint refclk control register of…
krishnachaitanya-linux May 27, 2025
171bdfa
FROMLIST: phy: qcom-qmp-pcie: Add support for keeping refclk always on
krishnachaitanya-linux May 27, 2025
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7 changes: 7 additions & 0 deletions Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,13 @@ properties:
"#phy-cells":
const: 0

qcom,refclk-always-on:
type: boolean
description: In some platform where PCIe switch is connected, pcie switch due to some design
limitation fails to propage clkreq signal to the host and due to that host will not send
refclk, which results in linkdown in L1.2 or L1.1 exit initiated by EP.
This property if set keeps refclk always on even in Low power states.

required:
- compatible
- reg
Expand Down
39 changes: 36 additions & 3 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,8 @@
#include "phy-qcom-qmp-pcie-qhp.h"

#define PHY_INIT_COMPLETE_TIMEOUT 10000
/* PCS_PCIE_ENDPOINT_REFCLK_CNTRL */
#define EPCLK_ALWAYS_ON_EN BIT(6)

/* set of registers with offsets different per-PHY */
enum qphy_reg_layout {
Expand All @@ -47,6 +49,7 @@ enum qphy_reg_layout {
QPHY_START_CTRL,
QPHY_PCS_STATUS,
QPHY_PCS_POWER_DOWN_CONTROL,
QPHY_PCS_ENDPOINT_REFCLK_CNTRL,
/* Keep last to ensure regs_layout arrays are properly initialized */
QPHY_LAYOUT_SIZE
};
Expand All @@ -63,6 +66,7 @@ static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
[QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL,
};

static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
Expand All @@ -77,13 +81,15 @@ static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
[QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL,
};

static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
[QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL,
};

static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
Expand All @@ -93,6 +99,22 @@ static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
};

static const unsigned int pciephy_v5_20_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V5_20_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V5_20_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V5_20_PCS_PCS_STATUS1,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_20_PCS_POWER_DOWN_CONTROL,
[QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL,
};

static const unsigned int pciephy_v6_20_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V6_20_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V6_20_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V6_20_PCS_PCS_STATUS1,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_20_PCS_POWER_DOWN_CONTROL,
[QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL,
};

static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
Expand Down Expand Up @@ -3061,6 +3083,7 @@ struct qmp_pcie {
struct phy *phy;
int mode;

bool refclk_always_on;
struct clk_fixed_rate pipe_clk_fixed;
struct clk_fixed_rate aux_clk_fixed;
};
Expand Down Expand Up @@ -3957,7 +3980,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = pciephy_v5_regs_layout,
.regs = pciephy_v5_20_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS_4_20,
Expand Down Expand Up @@ -4016,7 +4039,7 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.vreg_list = sm8550_qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
.regs = pciephy_v6_regs_layout,
.regs = pciephy_v6_20_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS_4_20,
Expand Down Expand Up @@ -4098,7 +4121,7 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = pciephy_v5_regs_layout,
.regs = pciephy_v5_20_regs_layout,

.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
.phy_status = PHYSTATUS_4_20,
Expand Down Expand Up @@ -4324,6 +4347,10 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num);

if (qmp->refclk_always_on && cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL])
qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL],
EPCLK_ALWAYS_ON_EN);

if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,
cfg->serdes_4ln_num);
Expand Down Expand Up @@ -4929,6 +4956,12 @@ static int qmp_pcie_probe(struct platform_device *pdev)
if (ret)
goto err_node_put;

qmp->refclk_always_on = of_property_read_bool(dev->of_node, "qcom,refclk-always-on");
if (qmp->refclk_always_on && !qmp->cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL]) {
dev_err(dev, "refclk is always on is present but refclk cntrl offset is not present\n");
goto err_node_put;
}

ret = qmp_pcie_register_clocks(qmp, np);
if (ret)
goto err_node_put;
Expand Down
1 change: 1 addition & 0 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
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Expand Up @@ -11,6 +11,7 @@
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x24
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
Expand Down
1 change: 1 addition & 0 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
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Expand Up @@ -9,6 +9,7 @@
/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x020
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
Expand Down
1 change: 1 addition & 0 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
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Expand Up @@ -10,6 +10,7 @@
#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL 0x020
#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0
Expand Down
4 changes: 4 additions & 0 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h
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Expand Up @@ -6,6 +6,10 @@
#ifndef QCOM_PHY_QMP_PCS_V5_20_H_
#define QCOM_PHY_QMP_PCS_V5_20_H_

#define QPHY_V5_20_PCS_SW_RESET 0x000
#define QPHY_V5_20_PCS_PCS_STATUS1 0x014
#define QPHY_V5_20_PCS_POWER_DOWN_CONTROL 0x040
#define QPHY_V5_20_PCS_START_CONTROL 0x044
#define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
#define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
Expand Down
4 changes: 4 additions & 0 deletions drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
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Expand Up @@ -7,6 +7,10 @@
#define QCOM_PHY_QMP_PCS_V6_20_H_

/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
#define QPHY_V6_20_PCS_SW_RESET 0x000
#define QPHY_V6_20_PCS_PCS_STATUS1 0x014
#define QPHY_V6_20_PCS_POWER_DOWN_CONTROL 0x040
#define QPHY_V6_20_PCS_START_CONTROL 0x044
#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
Expand Down