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debug stub fixes, MMU log tweak #90

Merged
merged 5 commits into from
Jul 8, 2024
Merged

debug stub fixes, MMU log tweak #90

merged 5 commits into from
Jul 8, 2024

Commits on Jul 2, 2024

  1. Hexagon: lldb read/write predicate registers p0/p1/p2/p3 

    Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
    @taylorsimpson @androm3da
    taylorsimpson authored and androm3da committed Jul 2, 2024
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  2. Fix typo in hexagon-sys.xml 

    Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
    @taylorsimpson @androm3da
    taylorsimpson authored and androm3da committed Jul 2, 2024
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  3. Hexagon (target/hexagon) print new mode on mode change 

    Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
    @taylorsimpson @androm3da
    taylorsimpson authored and androm3da committed Jul 2, 2024
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  4. Hexagon (target/hexagon) optimize gen_read_greg 

    gregs 0-3 don't need special handling, so generate a TCG move
instead of calling a helper

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
    @taylorsimpson @androm3da
    taylorsimpson authored and androm3da committed Jul 2, 2024
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  5. Fix system/guest registers in hexagon-sys.xml 

    Add system registers to a total of 85 (per hex_regs.h)
Move guest registers to end
Add gelr/gsr/gosp/gbadva names for g0-g4

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
    @taylorsimpson @androm3da
    taylorsimpson authored and androm3da committed Jul 2, 2024
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