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target/riscv: Don't assert in riscv013_get_register() #916

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Sep 14, 2023
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7 changes: 5 additions & 2 deletions src/target/riscv/riscv.c
Original file line number Diff line number Diff line change
Expand Up @@ -4945,8 +4945,11 @@ int riscv_get_register(struct target *target, riscv_reg_t *value,
*/
int riscv_save_register(struct target *target, enum gdb_regno regid)
{
assert(target->state == TARGET_HALTED &&
"Doesn't make sense to populate register cache on non-halted targets.");
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "Can't save register %s on a hart that is not halted.",
gdb_regno_name(regid));
Comment on lines +4949 to +4950
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@JanMatCodasip JanMatCodasip Sep 14, 2023

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If you like, the state of the target can be part of the error message. This can help in future with log analysis and troubleshooting.

Suggested change
LOG_TARGET_ERROR(target, "Can't save register %s on a hart that is not halted.",
gdb_regno_name(regid));
LOG_TARGET_ERROR(target, "Can't save register %s on a hart that is not halted (current state: %s).",
gdb_regno_name(regid), target_state_name(target));

return ERROR_FAIL;
}
assert(gdb_regno_cacheable(regid, /* is write? */ false) &&
"Only cacheable registers can be saved.");

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