Merge pull request #114 from riscv-software-src/AFOliveira/mergeInstr…

…uctions

Merged F extension instructions. Some fields are not populated

arch/csr/fcsr.yaml → arch/csr/F/fcsr.yaml

@@ -1,4 +1,4 @@
-# yaml-language-server: $schema=../../schemas/csr_schema.json
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
 
 fcsr:
   long_name: Floating-point control and status register (`frm` + `fflags`)
@@ -93,7 +93,7 @@ fcsr:
   length: 32
   definedBy: F
   fields:
-    RMODE:
+    FRM:
       location: 7-5
       description: |
         Rounding modes are encoded as follows:
@@ -179,4 +179,4 @@ fcsr:
         Set by hardware when a floating point operation is inexact and stays set until explicitly
         cleared by software.
       type: RW-H
-      reset_value: UNDEFINED_LEGAL
+      reset_value: UNDEFINED_LEGAL

arch/ext/F.yaml

@@ -239,6 +239,20 @@ F:
         Indicates whether or not the `F` extension can be disabled with the `misa.F` bit.
       schema:
         type: boolean
+    HW_MSTATUS_FS_DIRTY_UPDATE:
+      description: |
+        Indicates whether or not hardware will write to `mstatus.FS`
+
+        Values are:
+        [separator="!"]
+        !===
+        h! none  ! Hardware never writes `mstatus.FS`
+        h! precise  ! Hardware writes `mstatus.FS` to the Dirty (3) state precisely when F registers are modified
+        h! imprecise ! Hardware writes `mstatus.FS` imprecisely. This will result in a call to unpredictable() on any attempt to read `mstatus` or write FP state.
+        !===
+      schema:
+        type: string
+        enum: ["none", "precise", "imprecise"]
     MSTATUS_FS_LEGAL_VALUES:
       description: |
         The set of values that mstatus.FS will accept from a software write.
@@ -251,4 +265,7 @@ F:
         uniqueItems: true
       also_defined_in: S
       extra_validation: |
-        assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F)
+        assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F)
+
+        # if HW is writing FS, then Dirty (3) better be a supported value
+        assert MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "none")

arch/inst/F/fadd.s.yaml

@@ -0,0 +1,27 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fadd.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  assembly: fd, fs1, fs2, rm
+  encoding:
+    match: 0000000------------------1010011
+    variables:
+    - name: fs2
+      location: 24-20
+    - name: fs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: fd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+      

arch/inst/F/fclass.s.yaml

@@ -0,0 +1,73 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fclass.s:
+  long_name: Single-precision floating-point classify.
+  description: |
+      The `fclass.s` instruction examines the value in floating-point register
+      _fs1_ and writes to integer register _rd_ a 10-bit mask that indicates
+      the class of the floating-point number.
+      The format of the mask is described in the table below.
+      The corresponding bit in _rd_ will be set if the property is true and
+      clear otherwise.
+      All other bits in _rd_ are cleared.
+      Note that exactly one bit in rd will be set.
+      `fclass.s` does not set the floating-point exception flags.
+
+      .Format of result of `fclass` instruction.
+      [%autowidth,float="center",align="center",cols="^,<",options="header",]
+      |===
+      |_rd_ bit |Meaning
+      |0 |_rs1_ is latexmath:[$-\infty$].
+      |1 |_rs1_ is a negative normal number.
+      |2 |_rs1_ is a negative subnormal number.
+      |3 |_rs1_ is latexmath:[$-0$].
+      |4 |_rs1_ is latexmath:[$+0$].
+      |5 |_rs1_ is a positive subnormal number.
+      |6 |_rs1_ is a positive normal number.
+      |7 |_rs1_ is latexmath:[$+\infty$].
+      |8 |_rs1_ is a signaling NaN.
+      |9 |_rs1_ is a quiet NaN.
+      |===
+
+  definedBy: F
+  assembly: xd, fs1
+  encoding:
+    match: 111000000000-----001-----1010011
+    variables:
+    - name: fs1
+      location: 19-15
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: false
+  operation(): |
+    check_f_ok($encoding);
+
+    Bits<32> sp_value = f[fs1][31:0];
+
+    if (is_sp_neg_inf?(sp_value)) {
+      X[rd] = 1 << 0;
+    } else if (is_sp_neg_norm?(sp_value)) {
+      X[rd] = 1 << 1;
+    } else if (is_sp_neg_subnorm?(sp_value)) {
+      X[rd] = 1 << 2;
+    } else if (is_sp_neg_zero?(sp_value)) {
+      X[rd] = 1 << 3;
+    } else if (is_sp_pos_zero?(sp_value)) {
+      X[rd] = 1 << 4;
+    } else if (is_sp_pos_subnorm?(sp_value)) {
+      X[rd] = 1 << 5;
+    } else if (is_sp_pos_norm?(sp_value)) {
+      X[rd] = 1 << 6;
+    } else if (is_sp_pos_inf?(sp_value)) {
+      X[rd] = 1 << 7;
+    } else if (is_sp_signaling_nan?(sp_value)) {
+      X[rd] = 1 << 8;
+    } else {
+      assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value");
+      X[rd] = 1 << 9;
+    }        

arch/inst/F/fcvt.l.s.yaml

@@ -0,0 +1,26 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.l.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: xd, fs1, rm
+  encoding:
+    match: 110000000010-------------1010011
+    variables:
+    - name: fs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+      

arch/inst/F/fcvt.lu.s.yaml

@@ -0,0 +1,26 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.lu.s:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: xd, fs1, rm
+  encoding:
+    match: 110000000011-------------1010011
+    variables:
+    - name: fs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+      

arch/inst/F/fcvt.s.l.yaml

@@ -0,0 +1,26 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.l:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: fd, xs1, rm
+  encoding:
+    match: 110100000010-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: fd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+      

arch/inst/F/fcvt.s.lu.yaml

@@ -0,0 +1,26 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.lu:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  base: 64
+  assembly: fd, xs1, rm
+  encoding:
+    match: 110100000011-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: fd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+      

arch/inst/F/fcvt.s.w.yaml

@@ -0,0 +1,50 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.w:
+  long_name: Convert signed 32-bit integer to single-precision float
+  description: |
+    Converts a 32-bit signed integer in integer register _rs1_ into a floating-point number in
+    floating-point register _fd_.
+
+    All floating-point to integer and integer to floating-point conversion instructions round
+    according to the _rm_ field.
+    A floating-point register can be initialized to floating-point positive zero using
+    `fcvt.s.w rd, x0`, which will never set any exception flags.
+
+    All floating-point conversion instructions set the Inexact exception flag if the rounded
+    result differs from the operand value and the Invalid exception flag is not set.
+  definedBy: F
+  assembly: fd, xs1
+  encoding:
+    match: 110100000000-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: fd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: false
+  operation(): |
+    check_f_ok($encoding);
+
+    Bits<32> int_value = X[rs1];
+
+    Bits<1> sign = int_value[31];
+
+    RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
+
+    if ((int_value & 32'h7fff_ffff) == 0) {
+      X[fd] = (sign == 1) ? packToF32UI(1, 0x9E, 0) : 0;
+    } else {
+      Bits<32> absA = (sign == 1) ? -int_value : int_value;
+      X[fd] = softfloat_normRoundPackToF32( sign, 0x9C, absA, rounding_mode );
+    }
+
+    mark_f_state_dirty();
+

arch/inst/F/fcvt.s.wu.yaml

@@ -0,0 +1,25 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+fcvt.s.wu:
+  long_name: No synopsis available.
+  description: |
+      No description available.
+  definedBy: F
+  assembly: fd, xs1, rm
+  encoding:
+    match: 110100000001-------------1010011
+    variables:
+    - name: rs1
+      location: 19-15
+    - name: rm
+      location: 14-12
+    - name: fd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  data_independent_timing: true
+  operation(): |
+