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Add gdb xml register support.
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This allows gdb to read misa and set breakpoints.  This is a work in progress,
and has a number of obvious problems, incomplete csr support, wrong int reg
size for rv32, etc.
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Jim Wilson authored and Michael Clark committed Oct 2, 2018
1 parent 28fbf5c commit 1431b8b
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Showing 7 changed files with 150 additions and 12 deletions.
2 changes: 2 additions & 0 deletions configure
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Original file line number Diff line number Diff line change
Expand Up @@ -7044,12 +7044,14 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
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43 changes: 43 additions & 0 deletions gdb-xml/riscv-cpu.xml
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@@ -0,0 +1,43 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
<reg name="x0" bitsize="64"/>
<reg name="x1" bitsize="64"/>
<reg name="x2" bitsize="64"/>
<reg name="x3" bitsize="64"/>
<reg name="x4" bitsize="64"/>
<reg name="x5" bitsize="64"/>
<reg name="x6" bitsize="64"/>
<reg name="x7" bitsize="64"/>
<reg name="x8" bitsize="64"/>
<reg name="x9" bitsize="64"/>
<reg name="x10" bitsize="64"/>
<reg name="x11" bitsize="64"/>
<reg name="x12" bitsize="64"/>
<reg name="x13" bitsize="64"/>
<reg name="x14" bitsize="64"/>
<reg name="x15" bitsize="64"/>
<reg name="x16" bitsize="64"/>
<reg name="x17" bitsize="64"/>
<reg name="x18" bitsize="64"/>
<reg name="x19" bitsize="64"/>
<reg name="x20" bitsize="64"/>
<reg name="x21" bitsize="64"/>
<reg name="x22" bitsize="64"/>
<reg name="x23" bitsize="64"/>
<reg name="x24" bitsize="64"/>
<reg name="x25" bitsize="64"/>
<reg name="x26" bitsize="64"/>
<reg name="x27" bitsize="64"/>
<reg name="x28" bitsize="64"/>
<reg name="x29" bitsize="64"/>
<reg name="x30" bitsize="64"/>
<reg name="x31" bitsize="64"/>
<reg name="pc" bitsize="64"/>
</feature>
11 changes: 11 additions & 0 deletions gdb-xml/riscv-csr.xml
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.csr">
<reg name="misa" bitsize="64" regnum="0x342"/>
</feature>
43 changes: 43 additions & 0 deletions gdb-xml/riscv-fpu.xml
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@@ -0,0 +1,43 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.fpu">
<reg name="f0" bitsize="64"/>
<reg name="f1" bitsize="64"/>
<reg name="f2" bitsize="64"/>
<reg name="f3" bitsize="64"/>
<reg name="f4" bitsize="64"/>
<reg name="f5" bitsize="64"/>
<reg name="f6" bitsize="64"/>
<reg name="f7" bitsize="64"/>
<reg name="f8" bitsize="64"/>
<reg name="f9" bitsize="64"/>
<reg name="f10" bitsize="64"/>
<reg name="f11" bitsize="64"/>
<reg name="f12" bitsize="64"/>
<reg name="f13" bitsize="64"/>
<reg name="f14" bitsize="64"/>
<reg name="f15" bitsize="64"/>
<reg name="f16" bitsize="64"/>
<reg name="f17" bitsize="64"/>
<reg name="f18" bitsize="64"/>
<reg name="f19" bitsize="64"/>
<reg name="f20" bitsize="64"/>
<reg name="f21" bitsize="64"/>
<reg name="f22" bitsize="64"/>
<reg name="f23" bitsize="64"/>
<reg name="f24" bitsize="64"/>
<reg name="f25" bitsize="64"/>
<reg name="f26" bitsize="64"/>
<reg name="f27" bitsize="64"/>
<reg name="f28" bitsize="64"/>
<reg name="f29" bitsize="64"/>
<reg name="f30" bitsize="64"/>
<reg name="f31" bitsize="64"/>
<reg name="f32" bitsize="64"/>
</feature>
5 changes: 4 additions & 1 deletion target/riscv/cpu.c
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Expand Up @@ -312,6 +312,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}

riscv_cpu_register_gdb_regs_for_features(cs);

qemu_init_vcpu(cs);
cpu_reset(cs);

Expand Down Expand Up @@ -352,7 +354,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 65;
cc->gdb_num_core_regs = 33;
cc->gdb_core_xml_file = "riscv-cpu.xml";
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifdef CONFIG_USER_ONLY
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2 changes: 2 additions & 0 deletions target/riscv/cpu.h
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Expand Up @@ -346,6 +346,8 @@ typedef struct {
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);

void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);

#include "exec/cpu-all.h"

#endif /* RISCV_CPU_H */
56 changes: 45 additions & 11 deletions target/riscv/gdbstub.c
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Expand Up @@ -30,13 +30,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n == 32) {
return gdb_get_regl(mem_buf, env->pc);
} else if (n < 65) {
return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
} else if (n < 4096 + 65) {
target_ulong val = 0;
if (riscv_csrrw(env, n - 65, &val, 0, 0) == 0) {
return gdb_get_regl(mem_buf, val);
}
}
return 0;
}
Expand All @@ -55,14 +48,55 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n == 32) {
env->pc = ldtul_p(mem_buf);
return sizeof(target_ulong);
} else if (n < 65) {
env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
}
return 0;
}

static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
return gdb_get_reg64(mem_buf, env->fpr[n]);
}
return 0;
}

static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
} else if (n < 4096 + 65) {
}
return 0;
}

static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 4096) {
target_ulong val = 0;
if (riscv_csrrw(env, n, &val, 0, 0) == 0) {
return gdb_get_regl(mem_buf, val);
}
}
return 0;
}

static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
{
if (n < 4096) {
target_ulong val = ldtul_p(mem_buf);
if (riscv_csrrw(env, n - 65, NULL, val, -1) == 0) {
if (riscv_csrrw(env, n, NULL, val, -1) == 0) {
return sizeof(target_ulong);
}
}
return 0;
}

void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
/* ??? Assume all targets have FPU regs for now. */
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
32, "riscv-fpu.xml", 0);

gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-csr.xml", 0);
}

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