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SiFive CLIC (Core Level Interrupt Controller) test-beta1#157

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michaeljclark wants to merge 41 commits intoriscvarchive:qemu-for-upstreamfrom sifive:sifive-clic

+3,788-1,673

Commits on Jul 25, 2018

RISC-V: Update address bits to support sv39 and sv48
Michael Clark
committed
RISC-V: Improve page table walker spec compliance
Michael Clark
committed
RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
Michael Clark
committed
RISC-V: Simplify riscv_cpu_local_irqs_pending
Michael Clark
committed
RISC-V: Allow setting and clearing multiple irqs
Michael Clark
committed
RISC-V: Move non-ops from op_helper to cpu_helper
Michael Clark
committed
RISC-V: Update CSR and interrupt definitions
Michael Clark
committed
RISC-V: Implement modular CSR helper interface
Michael Clark
committed
RISC-V: Implement atomic mip/sip CSR updates
Michael Clark
committed
RISC-V: Implement existential predicates for CSRs
Michael Clark
committed
RISC-V: Split out mstatus_fs from tb_flags

rth7680
authored and
Michael Clark
committed
RISC-V: Mark mstatus.fs dirty

rth7680
and
Michael Clark
committed
RISC-V: Implement mstatus.TSR/TW/TVM

Michael Clark
and
msuozzo
committed
RISC-V: Add public API for the CSR dispatch table
Michael Clark
committed
RISC-V: Add hartid and \n to interrupt logging
Michael Clark
committed
RISC-V: Use riscv prefix consistently on cpu helpers
Michael Clark
committed
RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
Michael Clark
committed
RISC-V: Add missing free for plic_hart_config
Michael Clark
committed
RISC-V: Allow interrupt controllers to claim interrupts
Michael Clark
committed
RISC-V: Add misa to DisasContext
Michael Clark
committed
RISC-V: Add misa.MAFD checks to translate
Michael Clark
committed
RISC-V: Add misa runtime write support
Michael Clark
committed
RISC-V: Fix CLINT timecmp low 32-bit writes

Michael Clark
and
exokortex
committed
RISC-V: Fix PLIC pending bitfield reads
Michael Clark
committed
RISC-V: Enable second UART on sifive_e and sifive_u
Michael Clark
committed
RISC-V: Remove unnecessary disassembler constraints
Michael Clark
committed
elf: Add RISC-V PSABI ELF header defines
Michael Clark
committed
RISC-V: linux-user support for RVE ABI

kito-cheng
and
Michael Clark
committed
RISC-V: Don't add NULL bootargs to device-tree
Michael Clark
committed
RISC-V: Support separate firmware and kernel payload
Michael Clark
committed
RISC-V: Change local interrupts from edge to level
Michael Clark
committed
RISC-V: Add SiFive Test device to E and U series machines
Michael Clark
committed
RISC-V: Add support for vectored interrupts
Michael Clark
committed
RISC-V: Convert trap debugging to trace events
Michael Clark
committed
RISC-V: Update load reservation comment in do_interrupt
Michael Clark
committed
sifive_prci: Read and write PRCI registers

nategraff-sifive
authored and
Michael Clark
committed
sifive_uart: Implement interrupt pending register

nategraff-sifive
authored and
Michael Clark
committed
target/riscv/pmp.c: Fix PMP NAPOT decoding bug

dayeol
authored and
Michael Clark
committed
target/riscv/pmp.c: Fix PMP range boundary address bug

dayeol
authored and
Michael Clark
committed
riscv: remove define cpu_init()

Igor Mammedov
authored and
Michael Clark
committed

Commits on Sep 21, 2018

SiFive CLIC (Core Level Interrupt Controller) test-beta1
Michael Clark
committed