Add multiple registers and update fields

[bitboom]

I added the following registers by referring here.

Added registers

• CNTPOFF_EL2
• CPTR_EL2
• HPFAR_EL2
• ICC_CTLR_EL1
• ICC_SRE_EL2
• ICH_AP0R_EL2
• ICH_AP1R_EL2
• ICH_HCR_EL2
• ICH_LR_EL2
• ICH_MISR_EL2
• ICH_VMCR_EL2
• ICH_VTR_EL2
• ID_AA64AFR0_EL1
• ID_AA64AFR1_EL1
• ID_AA64DFR0_EL1
• ID_AA64DFR1_EL1
• ID_AA64ISAR1_EL1
• ID_AA64PFR0_EL1
• ID_AA64PFR1_EL1

Updated registers

• ESL_EL1
• HCR_EL2
• ICH_LR0_EL2
• SCTLR_EL2
• VTCR_EL2

[nchong-at-aws]

Thanks @bitboom . I'll review your changes.

[berkus]

Hmm, I don't see NMI field listed in the ARM

[nchong-at-aws]

I think we may need to agree on what version of the ARM we follow. This field does appear at least in Issue H of the Arm Generic Interrupt Controller (Arm IHI 0069H (ID020922)).

[berkus]

I am good with supporting the broadest range, and it already has a note "When FEAT_GICv3_NMI is implemented" so I guess that's good.

[berkus]

This can be converted into an enum, only 3 valid values for 4 available bits.

[berkus]

Looking at possible encodings it is probably safe to encode FIPA as OFFSET(0) NUMBITS(48).

[bitboom]

After taking a closer look, FIPA could be OFFSET(4) NUMBIT(48). It's a bit confusing when viewed on the web due to the indentation, but it's clearer in the PDF version.

This conditions below refer to an offset within the 44 bits of FIPA[47:4].

• NS, bit [63]
• Bits [62:48]
• FIPA, bits [47:4]
  • FIPA encoding when FEAT_D128 is implemented
    • FIPA, bits [43:0]: Bits [55:12] of the Faulting Intermediate Physical Address.
  • FIPA encoding when FEAT_LPA is implemented and FEAT_D128 is not implemented
    • Bits [43:40] Reserved, RES0.
    • FIPA, bits [39:0]: Bits [51:12] of the Faulting Intermediate Physical Address
  • FIPA encoding when FEAT_LPA is not implemented
    • Bits [43:36]: Reserved, RES0.
    • FIPA, bits [35:0]: Bits[47:12] of the Faulting Intermediate Physical Address.
• Bits [3:0]: Reserved, RES0.

[berkus]

Ah, alright, yeah that makes sense, it was a bit unclear in the web version.

[berkus]

@bitboom some nitpicks and one factual error in bitfield offset, otherwise looking good! Please fix at least the invalid OFFSET and we can merge this. Preferably implement enum values for these wide fields, as I see you've already done in some other registers. Thanks!

[bitboom]

@bitboom some nitpicks and one factual error in bitfield offset, otherwise looking good! Please fix at least the invalid OFFSET and we can merge this. Preferably implement enum values for these wide fields, as I see you've already done in some other registers. Thanks!

@berkus Thank you for the detailed review 😄 Most of the feedback has been reflected, and I've added a comment regarding the FIPA field. Let me know if you have any further feedback.