Add multiple registers and update fields

src/registers.rs

@@ -28,12 +28,14 @@ mod cntp_ctl_el0;
 mod cntp_cval_el0;
 mod cntp_tval_el0;
 mod cntpct_el0;
+mod cntpoff_el2;
 mod cntv_ctl_el0;
 mod cntv_cval_el0;
 mod cntv_tval_el0;
 mod cntvct_el0;
 mod cntvoff_el2;
 mod cpacr_el1;
+mod cptr_el2;
 mod csselr_el1;
 mod currentel;
 mod dacr32_el2;
@@ -52,7 +54,14 @@ mod far_el2;
 mod far_el3;
 mod fp;
 mod hcr_el2;
+mod hpfar_el2;
+mod icc_sre_el2;
+mod id_aa64afr0_el1;
+mod id_aa64afr1_el1;
+mod id_aa64dfr0_el1;
+mod id_aa64dfr1_el1;
 mod id_aa64isar0_el1;
+mod id_aa64isar1_el1;
 mod id_aa64mmfr0_el1;
 mod id_aa64mmfr1_el1;
 mod id_aa64mmfr2_el1;
@@ -116,12 +125,14 @@ pub use cntp_ctl_el0::CNTP_CTL_EL0;
 pub use cntp_cval_el0::CNTP_CVAL_EL0;
 pub use cntp_tval_el0::CNTP_TVAL_EL0;
 pub use cntpct_el0::CNTPCT_EL0;
+pub use cntpoff_el2::CNTPOFF_EL2;
 pub use cntv_ctl_el0::CNTV_CTL_EL0;
 pub use cntv_cval_el0::CNTV_CVAL_EL0;
 pub use cntv_tval_el0::CNTV_TVAL_EL0;
 pub use cntvct_el0::CNTVCT_EL0;
 pub use cntvoff_el2::CNTVOFF_EL2;
 pub use cpacr_el1::CPACR_EL1;
+pub use cptr_el2::CPTR_EL2;
 pub use csselr_el1::CSSELR_EL1;
 pub use currentel::CurrentEL;
 pub use dacr32_el2::DACR32_EL2;
@@ -140,7 +151,14 @@ pub use far_el2::FAR_EL2;
 pub use far_el3::FAR_EL3;
 pub use fp::FP;
 pub use hcr_el2::HCR_EL2;
+pub use hpfar_el2::HPFAR_EL2;
+pub use icc_sre_el2::ICC_SRE_EL2;
+pub use id_aa64afr0_el1::ID_AA64AFR0_EL1;
+pub use id_aa64afr1_el1::ID_AA64AFR1_EL1;
+pub use id_aa64dfr0_el1::ID_AA64DFR0_EL1;
+pub use id_aa64dfr1_el1::ID_AA64DFR1_EL1;
 pub use id_aa64isar0_el1::ID_AA64ISAR0_EL1;
+pub use id_aa64isar1_el1::ID_AA64ISAR1_EL1;
 pub use id_aa64mmfr0_el1::ID_AA64MMFR0_EL1;
 pub use id_aa64mmfr1_el1::ID_AA64MMFR1_EL1;
 pub use id_aa64mmfr2_el1::ID_AA64MMFR2_EL1;

src/registers/cntkctl_el1.rs

@@ -9,8 +9,8 @@
 //! Counter-timer Kernel Control register - EL1
 //!
 //! When FEAT_VHE is implemented and HCR_EL2.{E2H, TGE} is {1, 1}, this register does not
-//! cause any event stream from the virtual counter to be generated, and does not control access to the
-//! counters and timers. The access to counters and timers at EL0 is controlled by CNTHCTL_EL2.
+//! cause any event stream from the virtual counter to be generated, and does not control access to
+//! the counters and timers. The access to counters and timers at EL0 is controlled by CNTHCTL_EL2.
 //!
 //! When FEAT_VHE is not implemented, or when HCR_EL2.{E2H, TGE} is not {1, 1}, this register
 //! controls the generation of an event stream from the virtual counter, and access from EL0 to the

src/registers/cntpoff_el2.rs

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2024 by the author(s)
+//
+// Author(s):
+//   - Sangwan Kwon <sangwan.kwon@samsung.com>
+
+//! Counter-timer Physical Offset register - EL2
+//!
+//! Holds the 64-bit physical offset.
+//! This is the offset for the AArch64 physical timers and counters
+//! when Enhanced Counter Virtualization is enabled.
+
+use tock_registers::interfaces::{Readable, Writeable};
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "CNTPOFF_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_write_raw!(u64, "CNTPOFF_EL2", "x");
+}
+
+pub const CNTPOFF_EL2: Reg = Reg {};

src/registers/cptr_el2.rs

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2024 by the author(s)
+//
+// Author(s):
+//   - Sangwan Kwon <sangwan.kwon@samsung.com>
+
+//! Architectural Feature Trap Register - EL2
+//!
+//! Controls trapping to EL2 of accesses to CPACR, CPACR_EL1, trace, Activity Monitor, SME,
+//! Streaming SVE, SVE, and Advanced SIMD and floating-point functionality.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub CPTR_EL2 [
+        /// Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor
+        /// registers to EL2.
+        ///
+        /// 0 Accesses from EL1 and EL0 to Activity Monitor registers are not trapped.
+        ///
+        /// 1 Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2,
+        /// when EL2 is enabled in the current Security state.
+        TAM  OFFSET(30) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = CPTR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "CPTR_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = CPTR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "CPTR_EL2", "x");
+}
+
+pub const CPTR_EL2: Reg = Reg {};

src/registers/esr_el1.rs

@@ -84,7 +84,7 @@ impl Readable for Reg {
 
 impl Writeable for Reg {
     type T = u64;
-    type R = ();
+    type R = ESR_EL1::Register;
 
     sys_coproc_write_raw!(u64, "ESR_EL1", "x");
 }

src/registers/hcr_el2.rs

@@ -66,6 +66,21 @@ register_bitfields! {u64,
             EnableTrapSyncExtAbortsToEl2 = 1,
         ],
 
+        /// Trap accesses of Error Record registers. Enables a trap to EL2 on accesses of
+        /// Error Record registers.
+        ///
+        /// 0 Accesses of the specified Error Record registers are not trapped by this mechanism.
+        /// 1 Accesses of the specified Error Record registers at EL1 are trapped to EL2,
+        ///   unless the instruction generates a higher priority exception.
+        TERR  OFFSET(36) NUMBITS(1) [],
+
+        /// Trap LOR registers. Traps Non-secure EL1 accesses to LORSA_EL1, LOREA_EL1, LORN_EL1,
+        /// LORC_EL1, and LORID_EL1 registers to EL2.
+        ///
+        /// 0 This control does not cause any instructions to be trapped.
+        /// 1 Non-secure EL1 accesses to the LOR registers are trapped to EL2.
+        TLOR  OFFSET(35) NUMBITS(1) [],
+
         /// EL2 Host. Enables a configuration where a Host Operating System is running in EL2, and
         /// the Host Operating System's applications are running in EL0.
         E2H   OFFSET(34) NUMBITS(1) [
@@ -128,6 +143,41 @@ register_bitfields! {u64,
             EnableTrapGeneralExceptionsToEl2 = 1,
         ],
 
+        /// Trap data or unified cache maintenance instructions that operate by Set/Way.
+        /// Traps execution of those cache maintenance instructions at EL1 to EL2, when
+        /// EL2 is enabled in the current Security state.
+        ///
+        /// 0 This control does not cause any instructions to be trapped.
+        /// 1 Execution of the specified instructions is trapped to EL2, when EL2 is enabled
+        /// in the current Security state.
+        TSW   OFFSET(22) NUMBITS(1) [],
+
+        /// Trap Auxiliary Control Registers. Traps EL1 accesses to the Auxiliary Control Registers
+        /// to EL2, when EL2 is enabled in the current Security state
+        ///
+        /// 0 This control does not cause any instructions to be trapped.
+        /// 1 EL1 accesses to the specified registers are trapped to EL2, when EL2 is enabled in the
+        ///   current Security state.
+        TACR  OFFSET(21) NUMBITS(1) [],
+
+        /// Trap IMPLEMENTATION DEFINED functionality. Traps EL1 accesses to the encodings reserved
+        /// for IMPLEMENTATION DEFINED functionality to EL2, when EL2 is enabled in the current
+        /// Security state
+        ///
+        /// 0 This control does not cause any instructions to be trapped.
+        /// 1 EL1 accesses to or execution of the specified encodings reserved for IMPLEMENTATION
+        /// DEFINED functionality are trapped to EL2, when EL2 is enabled in the current Security
+        /// state.
+        TIDCP OFFSET(20) NUMBITS(1) [],
+
+        /// Trap ID group 3. Traps EL1 reads of group 3 ID registers to EL2, when EL2 is enabled
+        /// in the current Security state.
+        ///
+        /// 0 This control does not cause any instructions to be trapped.
+        /// 1 The specified EL1 read accesses to ID group 3 registers are trapped to EL2, when EL2
+        /// is enabled in the current Security state.
+        TID3  OFFSET(18) NUMBITS(1) [],
+
         /// Trap SMC instructions. Traps EL1 execution of SMC instructions to EL2, when EL2 is
         /// enabled in the current Security state.
         ///
@@ -196,6 +246,23 @@ register_bitfields! {u64,
         /// field behaves as 0 for all purposes other than a direct read of the value of this field.
         DC   OFFSET(12) NUMBITS(1) [],
 
+        /// Barrier Shareability upgrade. This field determines the minimum shareability domain that
+        /// is applied to any barrier instruction executed from EL1 or EL0.
+        BSU  OFFSET(10) NUMBITS(2) [
+            NoEffect = 0b00,
+            InnerShareable = 0b01,
+            OuterShareable = 0b10,
+            FullSystem = 0b11
+        ],
+
+        /// Force broadcast. Causes the following instructions to be broadcast within the Inner
+        /// Shareable domain when executed from EL1.
+        ///
+        /// 0 This field has no effect on the operation of the specified instructions.
+        /// 1 When one of the specified instruction is executed at EL1, the instruction is broadcast
+        /// within the Inner Shareable shareability domain.
+        FB    OFFSET(9) NUMBITS(1) [],
+
         /// Physical SError interrupt routing.
         ///   - If bit is 1 when executing at any Exception level, and EL2 is enabled in the current
         ///     Security state:

src/registers/hpfar_el2.rs

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2024 by the author(s)
+//
+// Author(s):
+//   - Sangwan Kwon <sangwan.kwon@samsung.com>
+
+//! Hypervisor IPA Fault Address Register - EL2
+//!
+//! Holds the faulting IPA for some aborts on a stage 2 translation taken to EL2.
+
+use tock_registers::{interfaces::Readable, register_bitfields};
+
+register_bitfields! {u64,
+    pub HPFAR_EL2 [
+        /// Faulting IPA address space.
+        NS   OFFSET(63) NUMBITS(1) [],
+
+        /// Faulting Intermediate Physical Address.
+        FIPA OFFSET(4) NUMBITS(40) []
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = HPFAR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "HPFAR_EL2", "x");
+}
+
+pub const HPFAR_EL2: Reg = Reg {};

src/registers/icc_sre_el2.rs

@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2024 by the author(s)
+//
+// Author(s):
+//   - Sangwan Kwon <sangwan.kwon@samsung.com>
+
+//! Interrupt Controller System Register Enable Register - EL2
+//!
+//! Controls whether the System register interface or the memory-mapped interface
+//! to the GIC CPU interface is used for EL2.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub ICC_SRE_EL2 [
+        /// Enables lower Exception level access to ICC_SRE_EL1.
+        ///
+        /// 0 When EL2 is implemented and enabled in the current Security state,
+        ///   EL1 accesses to ICC_SRE_EL1 trap to EL2.
+        ///
+        /// 1 EL1 accesses to ICC_SRE_EL1 do not trap to EL2.
+        ENABLE OFFSET(3) NUMBITS(1) [],
+
+        /// Disable IRQ bypass.
+        ///
+        /// 0 IRQ bypass enabled.
+        ///
+        /// 1 IRQ bypass disabled.
+        DIB    OFFSET(2) NUMBITS(1) [],
+
+        /// Disable FIQ bypass.
+        ///
+        /// 0 FIQ bypass enabled.
+        ///
+        /// 1 FIQ bypass disabled.
+        DFB    OFFSET(1) NUMBITS(1) [],
+
+        /// System Register Enable.
+        ///
+        /// 0 The memory-mapped interface must be used. Access at EL2 to any ICH_* or
+        /// ICC_* register other than ICC_SRE_EL1 or ICC_SRE_EL2, is trapped to EL2.
+        ///
+        /// 1 The System register interface to the ICH_* registers and the EL1 and EL2
+        /// ICC_* registers is enabled for EL2.
+        SRE    OFFSET(0) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ICC_SRE_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "ICC_SRE_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ICC_SRE_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "ICC_SRE_EL2", "x");
+}
+
+pub const ICC_SRE_EL2: Reg = Reg {};

src/registers/id_aa64afr0_el1.rs

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2024 by the author(s)
+//
+// Author(s):
+//   - Sangwan Kwon <sangwan.kwon@samsung.com>
+
+//! AArch64 Auxiliary Feature Register 0 - EL1
+//!
+//! Provides information about the IMPLEMENTATION DEFINED features of the PE in AArch64 state.
+
+use tock_registers::interfaces::Readable;
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "ID_AA64AFR0_EL1", "x");
+}
+
+pub const ID_AA64AFR0_EL1: Reg = Reg {};