Add thumbv8m.main support.

.travis.yml

@@ -22,6 +22,10 @@ matrix:
  rust: stable
  if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master)
 
+ - env: TARGET=thumbv8m.main-none-eabi
+ rust: stable
+ if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master)
+
  - env: TARGET=x86_64-unknown-linux-gnu
  rust: nightly
  if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master)
@@ -42,6 +46,10 @@ matrix:
  rust: nightly
  if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master)
 
+ - env: TARGET=thumbv8m.main-none-eabi
+ rust: nightly
+ if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master)
+
 before_install: set -e
 
 install:

Cargo.toml

@@ -19,10 +19,21 @@ autoexamples = true
 r0 = "0.2.2"
 cortex-m-rt-macros = { path = "macros", version = "0.1.5" }
 
+[target.thumbv7em-none-eabihf.dev-dependencies]
+cortex-m-semihosting = "0.3.1"
+
+[target.thumbv7em-none-eabi.dev-dependencies]
+cortex-m-semihosting = "0.3.1"
+
+[target.thumbv7m-none-eabi.dev-dependencies]
+cortex-m-semihosting = "0.3.1"
+
+[target.thumbv6m-none-eabi.dev-dependencies]
+cortex-m-semihosting = "0.3.1"
+
 [dev-dependencies]
-cortex-m = ">= 0.5.7, <0.7"
+cortex-m = "0.6"
 panic-halt = "0.2.0"
-cortex-m-semihosting = "0.3.1"
 
 [dev-dependencies.rand]
 default-features = false

assemble.sh

@@ -22,4 +22,7 @@ ar crs bin/thumbv7em-none-eabihf.a bin/$crate.o
 arm-none-eabi-as -march=armv8-m.base asm.s -o bin/$crate.o
 ar crs bin/thumbv8m.base-none-eabi.a bin/$crate.o
 
+arm-none-eabi-as -march=armv8-m.main asm.s -o bin/$crate.o
+ar crs bin/thumbv8m.main-none-eabi.a bin/$crate.o
+
 rm bin/$crate.o

build.rs

@@ -8,7 +8,6 @@ fn main() {
  let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
 
  has_fpu(&target);
- let is_armv6m = is_armv6m(&target);
 
  if target.starts_with("thumbv") {
  fs::copy(
@@ -43,7 +42,23 @@ INCLUDE device.x"#
  f
  };
 
- let max_int_handlers = if is_armv6m { 32 } else { 240 };
+ let max_int_handlers = if target.starts_with("thumbv6m-") {
+ println!("cargo:rustc-cfg=cortex_m");
+ println!("cargo:rustc-cfg=armv6m");
+ 32
+ } else if target.starts_with("thumbv7m-") || target.starts_with("thumbv7em-") {
+ println!("cargo:rustc-cfg=cortex_m");
+ println!("cargo:rustc-cfg=armv7m");
+ 240
+ } else if target.starts_with("thumbv8m") {
+ println!("cargo:rustc-cfg=cortex_m");
+ println!("cargo:rustc-cfg=armv8m");
+ 240
+ } else {
+ // Non ARM target. We assume you're just testing the syntax.
+ // This value seems as soon as any
+ 240
+ };
 
  // checking the size of the interrupts portion of the vector table is sub-architecture dependent
  writeln!(
@@ -58,6 +73,10 @@ handlers.");
  max_int_handlers
  ).unwrap();
 
+ if target.ends_with("-eabihf") {
+ println!("cargo:rustc-cfg=has_fpu");
+ }
+
  println!("cargo:rustc-link-search={}", out.display());
 
  println!("cargo:rerun-if-changed=build.rs");
@@ -69,12 +88,3 @@ fn has_fpu(target: &str) {
  println!("cargo:rustc-cfg=has_fpu");
  }
 }
-
-fn is_armv6m(target: &str) -> bool {
- if target.starts_with("thumbv6m-") {
- println!("cargo:rustc-cfg=armv6m");
- true
- } else {
- false
- }
-}

examples/qemu.rs

@@ -2,28 +2,39 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m;
 
+extern crate cortex_m;
 extern crate cortex_m_rt as rt;
+
+#[cfg(not(armv8m))]
 extern crate cortex_m_semihosting as semihosting;
+
 extern crate panic_halt;
 
-use core::fmt::Write;
 use cortex_m::asm;
 use rt::entry;
 
+#[cfg(not(armv8m))]
 #[entry]
 fn main() -> ! {
+ use core::fmt::Write;
  let x = 42;
 
  loop {
  asm::nop();
 
  // write something through semihosting interface
  let mut hstdout = semihosting::hio::hstdout().unwrap();
- write!(hstdout, "x = {}\n", x);
-
+ write!(hstdout, "x = {}\n", x).unwrap();
  // exit from qemu
  semihosting::debug::exit(semihosting::debug::EXIT_SUCCESS);
  }
 }
+
+#[cfg(armv8m)]
+#[entry]
+fn main() -> ! {
+ loop {
+ asm::nop();
+ }
+}