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@minxuanz minxuanz commented Aug 8, 2025

see https://go-review.googlesource.com/c/go/+/526659, All of riscv CPU using 64B for cache-line size.

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rustbot commented Aug 8, 2025

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@rustbot rustbot added S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-libs Relevant to the library team, which will review and decide on the PR/issue. labels Aug 8, 2025
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Confirmed by looking at all readily available implementations.

@bors try jobs=dist-riscv64-linux

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rust-bors bot added a commit that referenced this pull request Aug 26, 2025
Fix wrong cache line size of riscv64

try-job: dist-riscv64-linux
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rust-bors bot commented Aug 26, 2025

☀️ Try build successful (CI)
Build commit: a359786 (a3597869fc4b44a6cd714ccf674fc1e1996d8fe9, parent: 91ee6a4057ce4bf1ab6d2f932cae497488d67c81)

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@bors r+ rollup=always

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bors commented Aug 26, 2025

📌 Commit d47b5e4 has been approved by samueltardieu

It is now in the queue for this repository.

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Aug 26, 2025
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a4lg commented Aug 27, 2025

+1 (no changes required) except that "wrong" in the title seems a bit misleading (so I'll leave a note here).

The RISC-V architecture (itself) defines nothing about cache line size (in fact, we don't actually need cache in the minimal configuration).

However, for baseline purposes, there's RISC-V Profiles specification1.
In that specification, profiles for application-class processor environment, RVA22U64/S64 and RVA23U64/S64 mandate that the Zic64b extension must be present (i.e. cache block size must be exactly 64-bytes and must be naturally aligned).

Footnotes

  1. For instance, Ubuntu 25.10 will require RVA23U64/S64 baseline.

bors added a commit that referenced this pull request Aug 27, 2025
Rollup of 6 pull requests

Successful merges:

 - #142215 (Use -Zmir-opt-level=0 in tests for MIR building)
 - #143341 (Mention that casting to *const () is a way to roundtrip with from_raw_parts)
 - #145078 (Fix wrong cache line size of riscv64)
 - #145290 (Improve std::fs::read_dir docs)
 - #145335 (Move WTF-8 code from std into core and alloc)
 - #145904 (Move `riscv64-gc-unknown-linux-musl` from Tier 2 with Host tools to Tier 2)

r? `@ghost`
`@rustbot` modify labels: rollup
@bors bors merged commit 7879cbb into rust-lang:master Aug 27, 2025
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@rustbot rustbot added this to the 1.91.0 milestone Aug 27, 2025
rust-timer added a commit that referenced this pull request Aug 27, 2025
Rollup merge of #145078 - minxuanz:riscv-cacheline, r=samueltardieu

Fix wrong cache line size of riscv64

see https://go-review.googlesource.com/c/go/+/526659,  All of riscv CPU using 64B for cache-line size.
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6 participants