Computer Concepts Wild Vision Lark

Register map

IOC Address map:
  0000        : XC3030 FPGA (write)
            bit 0 - DIN
            bit 1 - CCLK
            bit 2 - INIT?  bits 2 & 3 may be reversed
            bit 3 - RESET?
  0000 - 1fff : banked ROM (read)
  2000        : ROM page register
  3000        : FPGA? 
    3000 read : IRQ status (/clear?)
            bit 0 - IRQ master
            bit 1 - AD1848 IRQ
            bit 2 - 16550 IRQ
            bit 6 - output FIFO half empty
            bit 7 - ~input FIFO half full
    3000 write :
            bit 3 - enable output FIFO
            bit 4 - enable input FIFO?
            bit 7 - reset?
  3400        : 16550 serial
  3c00 - 3c0f : AD1848 CODEC

MEMC Address map:
  0000 : Write to output FIFO
  0000 : Read from input FIFO

Basic design

Lark uses an AD1848 (WSS-compatible) CODEC connected to two AM7202A 1024x9 FIFOs - one for input, one for output. The FIFOs are 1024x9, these are used as 512x16 with the FPGA converting one 16-bit MEMC access to 2 8-bit FIFO accesses (and vice versa).

The Lark driver doesn't seem to use the AD1848 IRQ, just clearing the IRQ state. Instead the FIFO half-full flags are connected to interrupt lines and are used to trigger CPU transfers to and from the FIFOs.

The FPGA seems to implement a single read and single write port at 0x3000. Read is IRQ status, writing acts as control. Control seems to include enable bits for AD1848 DMA transfers to/from the FIFOs, and also a reset bit? There are several other bits that I haven't figured out the meaning of yet.

Internal Arc speaker is connected to one of the aux inputs, I am not sure which one. LK13 is connected to the other.

MIDI is just handled by a standard 16550, same as the MIDI Max and many other MIDI podules.

Links

Chris's Acorns: Computer Concepts Lark