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Initial FPGA Support #40

Merged
merged 283 commits into from
Jun 11, 2021
Merged

Initial FPGA Support #40

merged 283 commits into from
Jun 11, 2021

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TizianoDeMatteis
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@TizianoDeMatteis TizianoDeMatteis commented Mar 13, 2021

This PR includes several ONNX Node expansions specifically tailored for FPGA, in particular IntelFPGA.

daceml/onnx/op_implementations/pure_implementations.py Outdated Show resolved Hide resolved
daceml/onnx/shape_inference/symbolic_shape_infer.py Outdated Show resolved Hide resolved
daceml/transformation/input_to_constant.py Outdated Show resolved Hide resolved
Comment on lines +121 to +140
queue = deque([old_edge_in_shape.src])
while len(queue) > 0:
current_node = queue.popleft()

edges = state.in_edges(current_node)
state.remove_node(current_node)
for e in edges:
next_node = e.src
if len(state.out_edges(next_node)) == 0:
queue.append(next_node)

# get the edges between the the access_node and the nsdfg_node
old_edges = [
e for e in state.out_edges(access_node) if e.dst == nsdfg_node
]

for edge in old_edges:
state.add_edge(old_edge_in.src, old_edge_in.src_conn, edge.dst,
edge.dst_conn, old_edge_in.data)
state.remove_edge(edge)
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looks a bit excessive here. There are only ever two edges and that's it.

daceml/util/utils.py Show resolved Hide resolved
daceml/util/utils.py Outdated Show resolved Hide resolved
@@ -0,0 +1,89 @@
"""
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what do you mean by the name "plot" in the filename

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plot_ is the default prefix used by sphinx gallery. We can change it if we want, suggestions welcome.

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ok, what do you think about demo_?

tests/transformation/test_input_to_constant.py Outdated Show resolved Hide resolved
@orausch
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orausch commented May 21, 2021

@TizianoDeMatteis Seems like the main reason for the bad coverage is because reshape elimination is not tested

.github/workflows/cpu-ci.yml Outdated Show resolved Hide resolved
@tbennun tbennun merged commit 1485743 into master Jun 11, 2021
@tbennun tbennun deleted the transformers_fpga branch June 11, 2021 16:45
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4 participants