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Initial FPGA Support #40

Merged
merged 283 commits into from
Jun 11, 2021
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7440c32
Add pure reshape
orausch Nov 28, 2020
1a09935
Remove ONNXRuntime environment from pure expansions
orausch Nov 28, 2020
31226fd
Switch reshape in_desc
orausch Nov 30, 2020
cb16334
Add LogSoftmax op and lenet MNIST example
orausch Dec 1, 2020
88610f1
Formatting
orausch Dec 2, 2020
ea5884b
Reduce codecov diff target
orausch Dec 2, 2020
ca14593
Move image ops to own file
orausch Dec 4, 2020
b20d402
Add Im2Col Convolution implementation
orausch Dec 8, 2020
c76028b
Add softmax to end of evaluation softmax
orausch Dec 9, 2020
cb04cf2
Merged lenet5
TizianoDeMatteis Dec 10, 2020
db382bb
GEMM test: 3 layers
TizianoDeMatteis Dec 10, 2020
4a278c9
im2col Conv: first implementation, works only with B=1
TizianoDeMatteis Dec 10, 2020
4a17487
Im2Col conv: working with multiple batches
TizianoDeMatteis Dec 10, 2020
90c106b
Add LeNet test
orausch Nov 26, 2020
7f41f2d
Add basic pure conv implementation
orausch Nov 27, 2020
4551c17
Initialize Y before the conv
orausch Nov 27, 2020
a492d7d
Add MaxPool operator
orausch Nov 27, 2020
12f25f7
Add ReLU and Gemm
orausch Nov 27, 2020
71d2d0a
Add pure reshape
orausch Nov 28, 2020
7f43475
Remove ONNXRuntime environment from pure expansions
orausch Nov 28, 2020
dbcdd0d
Switch reshape in_desc
orausch Nov 30, 2020
ebb5489
Add LogSoftmax op and lenet MNIST example
orausch Dec 1, 2020
c274c52
Formatting
orausch Dec 2, 2020
355b049
Reduce codecov diff target
orausch Dec 2, 2020
4f0c69a
Move image ops to own file
orausch Dec 4, 2020
f71ae76
Add Im2Col Convolution implementation
orausch Dec 8, 2020
a38106d
Add softmax to end of evaluation softmax
orausch Dec 9, 2020
a08623a
Convert data nodes, update relu
TizianoDeMatteis Dec 11, 2020
8009ab3
Fix
TizianoDeMatteis Dec 11, 2020
2052574
Add InputToConstant transformation (no support for nested sdfgs yet)
orausch Dec 12, 2020
bbc25d2
Move data shape transformation to util
Dec 12, 2020
7097be9
Add ReshapeElimination transformation
orausch Dec 12, 2020
b5c3726
Convert access nodes to vectorized type for conv
Dec 12, 2020
ac8d1dd
Merged lenet5 branch
Dec 12, 2020
df15f0c
Conv: vectorized output
Dec 12, 2020
3e0111a
Make InputToConstant support nested SDFGs
orausch Dec 13, 2020
23fced3
Test streaming, prune connectors
Dec 14, 2020
3ee5f98
Inline SDFG
Dec 14, 2020
e6a598d
Merge branch 'lenet5' into lenet5_fpga
Dec 14, 2020
d312f70
Softmax FPGA, first impl
Dec 14, 2020
6a9d563
Test input to constat, add FPGA
Dec 14, 2020
f404576
Reshape elimination
Dec 14, 2020
49c9d49
Reshape elimination
Dec 14, 2020
a77522b
Make InputToConstant support multiple states
orausch Dec 14, 2020
1dff7d9
Test input to constant, inlined
Dec 14, 2020
608f7ef
Apply input to constant
Dec 14, 2020
b009dcc
Lenet with InputToConstant
Dec 14, 2020
66936fe
Removed debug prints
Dec 14, 2020
850ef93
Merge branch 'lenet5_fpga' into lenet5_fpga_vectorized_conv
Dec 14, 2020
bb12f1c
Relu, name matching for streaming
Dec 14, 2020
49b1635
Apply InputToConstant only for gemm
orausch Dec 14, 2020
43e6a42
InputToConstant for the last one only
Dec 14, 2020
8971292
One streaming composition
Dec 14, 2020
8830001
Only first conv and relu for streaming
Dec 14, 2020
a5995bc
InputToConstant for FC and Conv
Dec 15, 2020
a37de23
Streaming MaxPool
Dec 15, 2020
b69d4d0
Streaming max pool and test
Dec 15, 2020
af7f1bc
Lenet: streaming, started
Dec 15, 2020
e82844f
Lenet streaming composition
Dec 15, 2020
60d43a4
Softmax lenet
Dec 15, 2020
e59ef57
Lenet softmax
Dec 15, 2020
aaa75b3
InputToConstnt, apply repeated
Dec 15, 2020
5ee125a
Attempt for streaming GEMM
Dec 15, 2020
683433e
Added streaming composition GEMM-Relu
Dec 15, 2020
2d3ae80
Added streaming composition GEMM-Relu
Dec 15, 2020
1e60337
Fix softmax accumulator
Dec 15, 2020
b184023
Add pure pytorch execution
Dec 16, 2020
89e004c
Tests for perf debug: streaming conv -> relu
Dec 21, 2020
6783d1c
Test streaming, use input to constant
Dec 22, 2020
6d1678f
Test im2col conv
Dec 22, 2020
17aa18b
More consistent testing for conv im2col
Dec 22, 2020
f030ca8
Add state_fields for DaCe environements
Jan 11, 2021
eff5bb8
Conv: drain while compute
Jan 11, 2021
effd035
Explicit drain variables
Jan 13, 2021
ea4e9d0
Add patch for newast
Jan 13, 2021
0894439
Try to increase buffer depth
Jan 13, 2021
e69e962
Added fake dependencies for ordering (must be cleaned)
Jan 14, 2021
573f486
Immediate feeding of A
Jan 14, 2021
1c9d464
Added safe delay
Jan 14, 2021
9561276
Conv: double buffering
Jan 15, 2021
725f585
Single tasklet compute and drain
Jan 17, 2021
f885d89
Test gemm, apply vectorization
Jan 19, 2021
f5119cc
GEMM immediate feeding A
Jan 19, 2021
81ac079
Dynamic memlet for feeding A
Jan 19, 2021
eb6da00
Remove one channel
Jan 19, 2021
aa2c5d8
Test gemm, input to constant
Jan 20, 2021
cb2bf50
New im2col impl, with safe delay
Jan 21, 2021
3aaf5f8
Test streaming gemm
Jan 23, 2021
704e041
Apply streaming composition automatically
TizianoDeMatteis Jan 26, 2021
6c2f41e
Test relu
TizianoDeMatteis Jan 27, 2021
a08c05c
Test relu
TizianoDeMatteis Jan 27, 2021
5791652
MaxPool supporting vec width=1, cleanup of some test
TizianoDeMatteis Jan 28, 2021
2c3c656
Test conv-relu-maxpool
TizianoDeMatteis Jan 28, 2021
b77f657
Attempt: max pool, unroll compute along vect width
TizianoDeMatteis Jan 28, 2021
b810ff1
Test conv, add command line flag
TizianoDeMatteis Jan 28, 2021
ea2a124
Updated streaming test
TizianoDeMatteis Jan 29, 2021
492f08a
Test GEMM cleanup
TizianoDeMatteis Jan 29, 2021
3124180
Testing: added other options
TizianoDeMatteis Feb 1, 2021
07d661c
Conv: unroll if matrix is too narrow
TizianoDeMatteis Feb 2, 2021
7f28cae
Test gemm-softmax
TizianoDeMatteis Feb 2, 2021
6a4544b
Update test_gemm
TizianoDeMatteis Feb 2, 2021
5b6cc86
Test gemm-softmax
TizianoDeMatteis Feb 2, 2021
1650142
GEMM flattend loop
TizianoDeMatteis Feb 3, 2021
6ffeb8f
GEMM: minimum buffer space for II
TizianoDeMatteis Feb 3, 2021
890f5d5
Minor updates on tests
TizianoDeMatteis Feb 3, 2021
28b39a7
Unroll write to memory in Relu (Intel FPGA) if needed
TizianoDeMatteis Feb 4, 2021
f5fb180
Merge branch 'gemm_pipelined' into lenet5_fpga_vectorized_conv
TizianoDeMatteis Feb 12, 2021
92bcd68
Moved FPGA tests in a new folder
TizianoDeMatteis Feb 22, 2021
2810742
Remove old test
TizianoDeMatteis Feb 22, 2021
191e305
Added test matmul. Implementation Batched Matmul (3D)
TizianoDeMatteis Feb 23, 2021
dfc952a
Test matmul
TizianoDeMatteis Feb 23, 2021
c1baa0e
Matmul, support 3D-2D matmul
TizianoDeMatteis Feb 24, 2021
59a96df
Prevent MMM deadlocks for stretched matrices
TizianoDeMatteis Feb 25, 2021
b525fac
Reshape: explicitely support for MHA
TizianoDeMatteis Feb 25, 2021
3d99202
Softmax, support for MHA
TizianoDeMatteis Feb 25, 2021
9c62de7
Reduce SUM, MHA expansion
TizianoDeMatteis Feb 25, 2021
9fb7a2c
MHA test fpga
TizianoDeMatteis Feb 25, 2021
e6ab07b
Minor fixes
TizianoDeMatteis Feb 25, 2021
e5216f1
MatMul support for vectorization
TizianoDeMatteis Feb 26, 2021
a42b26a
Run standalone bert cpu encoder
TizianoDeMatteis Feb 27, 2021
d376e9c
MHA fpga use onnxruntime expansion for Cast
TizianoDeMatteis Feb 27, 2021
bb32431
Test BERT FPGA skeleton
TizianoDeMatteis Mar 1, 2021
23be149
Merge master
TizianoDeMatteis Mar 1, 2021
e92ae22
ORT session
TizianoDeMatteis Mar 1, 2021
28698bd
Missing ReLu
TizianoDeMatteis Mar 1, 2021
7ba2947
MHA added sizes for BERT large
TizianoDeMatteis Mar 1, 2021
81f8fc0
Merged master
TizianoDeMatteis Mar 2, 2021
69d5d7d
ATTN test, clean up
TizianoDeMatteis Mar 2, 2021
2c04d83
Comments
TizianoDeMatteis Mar 5, 2021
12b6799
MatMul, allow non vectorized writes of result
TizianoDeMatteis Mar 5, 2021
4382db5
Test attn fpga
TizianoDeMatteis Mar 5, 2021
00e26fd
Cleanup
TizianoDeMatteis Mar 6, 2021
3e58135
Pure implementations, cleanup
TizianoDeMatteis Mar 6, 2021
c9a6cc5
Cleanup for PR
TizianoDeMatteis Mar 6, 2021
8a1b2a8
Cleanup for PR
TizianoDeMatteis Mar 6, 2021
90e5bb6
Cleanup test Relu
TizianoDeMatteis Mar 8, 2021
b5cd972
Cleanup test Relu
TizianoDeMatteis Mar 8, 2021
468c925
MaxPool expansion cleanup
TizianoDeMatteis Mar 11, 2021
087a0ee
Reshape FPGA expansion: use views
TizianoDeMatteis Mar 11, 2021
fc624dc
ONNX type checking consider vector data type
TizianoDeMatteis Mar 13, 2021
9e708aa
Cleanup
TizianoDeMatteis Mar 13, 2021
e218fe6
Cleanup
TizianoDeMatteis Mar 13, 2021
c530555
Cleanup
TizianoDeMatteis Mar 13, 2021
35b6df7
Yapf
TizianoDeMatteis Mar 13, 2021
19fd39c
Additional flag for Dace program
TizianoDeMatteis Mar 19, 2021
0622b3a
Merge master. Fix minor things. Output is now a tensor and therefore …
TizianoDeMatteis Mar 19, 2021
2a58056
Merge branch 'master' into transformers_fpga
TizianoDeMatteis Mar 19, 2021
cbf9d51
Ignore test
TizianoDeMatteis Mar 22, 2021
7472b37
Merge branch 'transformers_fpga' of https://github.com/spcl/daceml in…
TizianoDeMatteis Mar 22, 2021
12cd527
Skip FPGA tests
TizianoDeMatteis Mar 22, 2021
42c7a6f
Remove wrong test
TizianoDeMatteis Mar 22, 2021
6364042
After constant folding, do not consider removed arrays
TizianoDeMatteis Mar 22, 2021
887886f
Update daceml/onnx/op_implementations/fpga_implementations.py
TizianoDeMatteis Mar 24, 2021
cd32bb5
Update tests/pytorch/fpga/test_reshape_fpga.py
TizianoDeMatteis Mar 25, 2021
0e35a3f
Merge branch 'master' into transformers_fpga
TizianoDeMatteis Mar 25, 2021
573b87b
Merged master
TizianoDeMatteis Mar 27, 2021
b915651
Merged, yapf, tests
TizianoDeMatteis Mar 27, 2021
3c57e0f
Cleanup
TizianoDeMatteis Mar 31, 2021
4d7591c
Upd matmul. Needs factorization
TizianoDeMatteis Mar 31, 2021
2ab59a8
Remove floor from tasklet
TizianoDeMatteis Apr 1, 2021
4273f86
Cleanup code
TizianoDeMatteis Apr 1, 2021
3bdb543
Merged master
Apr 19, 2021
a4e2326
Missing property
Apr 19, 2021
4869825
Changed import for auto opt
TizianoDeMatteis May 6, 2021
fe59cf1
Merge branch 'master' into transformers_fpga
TizianoDeMatteis May 6, 2021
c37a112
Remove unneeded file
TizianoDeMatteis May 6, 2021
7a26995
Do not use CPU im2col Conv expansion
TizianoDeMatteis May 6, 2021
f962752
Address PR comments
TizianoDeMatteis May 6, 2021
a4281ee
Address PR comments
TizianoDeMatteis May 6, 2021
3105771
Change op expansion decorator
TizianoDeMatteis May 6, 2021
f4d6501
Yapfed with 0.31
TizianoDeMatteis May 6, 2021
2b149ea
Remove useless imports
TizianoDeMatteis May 7, 2021
01ec766
Autodiff: prioritize pure implementations when expanding
orausch May 7, 2021
652da8f
FPGA Testing
TizianoDeMatteis May 7, 2021
4468ea7
Merge branch 'transformers_fpga' of https://github.com/spcl/daceml in…
TizianoDeMatteis May 7, 2021
8e52d64
Yapfed
TizianoDeMatteis May 7, 2021
fa9de67
GH Action for FPGA
TizianoDeMatteis May 7, 2021
a69d66f
GH Action for FPGA
TizianoDeMatteis May 7, 2021
80435b1
GH Action for FPGA
TizianoDeMatteis May 7, 2021
dcd8aba
GH Action for FPGA, fix coverage source
TizianoDeMatteis May 7, 2021
e24f597
Do not run FPGA tests in parallel
TizianoDeMatteis May 7, 2021
5760b12
Provisional fix, to check that FPGA CI runs
TizianoDeMatteis May 7, 2021
5f8a698
Provisional fix, to check that FPGA CI runs
TizianoDeMatteis May 7, 2021
43627d5
Intel FPGA CI fixes
TizianoDeMatteis May 7, 2021
0f54023
Intel FPGA CI fixes
TizianoDeMatteis May 7, 2021
8acc74b
Use pytest also for FPGA
TizianoDeMatteis May 10, 2021
742c818
Added tests for naive Conv2D
TizianoDeMatteis May 10, 2021
ae18415
Set Dace env variables
TizianoDeMatteis May 10, 2021
e9fef34
Merged master
TizianoDeMatteis May 11, 2021
c1451f5
Revert format changes to symbolic shape infer
TizianoDeMatteis May 11, 2021
fb97cc2
Address review comments
TizianoDeMatteis May 11, 2021
b7e5b8c
Merge branch 'master' into transformers_fpga
orausch May 11, 2021
4224b4a
FPGA test: remove default implementation settings
TizianoDeMatteis May 12, 2021
7ad0594
Yapf
TizianoDeMatteis May 12, 2021
3f44d53
TMP: skip fpga test dirs
TizianoDeMatteis May 12, 2021
7e75ef1
Revert changes
TizianoDeMatteis May 12, 2021
d703575
Import only when necessary
TizianoDeMatteis May 12, 2021
d478613
Merge branch 'master' into transformers_fpga
TizianoDeMatteis May 14, 2021
c50eab6
Misplaced import
TizianoDeMatteis May 14, 2021
cfacee0
Merge branch 'master' into transformers_fpga
TizianoDeMatteis May 16, 2021
d88561c
Merged master
TizianoDeMatteis May 17, 2021
3c2b1aa
FPGA tests: properly pass dummy args, and other minor fixes
TizianoDeMatteis May 17, 2021
04714a8
Make module codegen use the compiled SDFG, not the uncompiled one
orausch May 17, 2021
015b793
InputToConstant: Fixes for scalar constants and memlet path removal
tbennun May 17, 2021
1d0a215
InputToConstant: remove memlet paths of parent SDFGs
tbennun May 17, 2021
0be67e3
Recompile SDFG after FPGA transform
TizianoDeMatteis May 18, 2021
3e4c961
Slice operator
TizianoDeMatteis May 18, 2021
9d84431
Yapf
TizianoDeMatteis May 18, 2021
72ac28f
Merge branch 'master' into transformers_fpga
TizianoDeMatteis May 18, 2021
05ac3d8
Lenet-FPGA: Do not autoptimize
TizianoDeMatteis May 18, 2021
bf5d859
Disable CUDA in constant folding
orausch May 18, 2021
89787b2
Merge branch 'transformers_fpga' of https://github.com/spcl/daceml in…
TizianoDeMatteis May 18, 2021
556c0d2
Default value for KernelSession, cuda parameter
TizianoDeMatteis May 18, 2021
f95dc69
Slice: optional parameters
TizianoDeMatteis May 18, 2021
651ade6
Lenet FPGA example
TizianoDeMatteis May 18, 2021
5b4fd6a
Update fpga example
orausch May 18, 2021
6679c47
Don't build FPGA examples on non-FPGA machines
orausch May 18, 2021
c7e6bae
Merge master
TizianoDeMatteis May 19, 2021
fa0c217
Add docs-no-trigger action
orausch May 19, 2021
e443d55
FPGA Tests: use hook
TizianoDeMatteis May 19, 2021
6e2a4f0
Merge branch 'transformers_fpga' of https://github.com/spcl/daceml in…
TizianoDeMatteis May 19, 2021
b5131f1
Remove Leftover
TizianoDeMatteis May 19, 2021
1084992
Correct environment variables for FPGA example
orausch May 19, 2021
2829edc
FPGA Tests: reduce number
TizianoDeMatteis May 19, 2021
d5d9195
Merge branch 'transformers_fpga' of https://github.com/spcl/daceml in…
TizianoDeMatteis May 19, 2021
3e8a485
Use change_default in example (since examples share the same process)
orausch May 19, 2021
ab28468
Merge branch 'master' into transformers_fpga
TizianoDeMatteis May 20, 2021
42fdf0f
Address review comments
TizianoDeMatteis May 20, 2021
13f41f6
InpToConst test
TizianoDeMatteis May 20, 2021
ebcf752
Explicitely expand to Pure
TizianoDeMatteis May 20, 2021
8f1d754
Add debug print
TizianoDeMatteis May 21, 2021
2d7cdd9
Reshape Elimination Test
TizianoDeMatteis May 21, 2021
d7d405c
Cleanup MatMul FPGA expansion
May 21, 2021
e36fa84
Use fstring instead of format
May 21, 2021
533fcc1
Merged master
May 21, 2021
50dc14d
iscudastorage: consider also FPGAs
May 21, 2021
e791944
Merged master
May 23, 2021
eac19f1
Merged master
May 24, 2021
9bb682a
Debug CI
May 24, 2021
7bb99bf
Merged master
May 25, 2021
69ee343
CI, remove stdout
TizianoDeMatteis Jun 10, 2021
cb0da61
Explicitely disable CUDA for Reshape Elim Test
TizianoDeMatteis Jun 10, 2021
8acd5da
Run test reshape separately
TizianoDeMatteis Jun 10, 2021
1c07ec6
Revert "Run test reshape separately"
TizianoDeMatteis Jun 10, 2021
bf8f09f
No need to indicate reshape expansion type
TizianoDeMatteis Jun 10, 2021
0920339
Useless argument
TizianoDeMatteis Jun 10, 2021
8ead263
Add gpu parameter to test
TizianoDeMatteis Jun 11, 2021
cbbe6d2
...and also pass it to Dace Module
TizianoDeMatteis Jun 11, 2021
ce8d3c2
Skip test
TizianoDeMatteis Jun 11, 2021
6070334
Yapf
TizianoDeMatteis Jun 11, 2021
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2 changes: 1 addition & 1 deletion .github/workflows/cpu-ci.yml
Original file line number Diff line number Diff line change
@@ -54,7 +54,7 @@ jobs:
- name: Test with pytest
env:
ORT_RELEASE: ${{ github.workspace }}/onnxruntime-daceml-patched
PYTEST_ARGS: --cov=daceml --cov-report=term --cov-report xml --cov-config=.coveragerc -m "not slow" -m "not gpu"
PYTEST_ARGS: --cov=daceml --cov-report=term --cov-report xml --cov-config=.coveragerc -m "not slow and not fpga and not gpu"
run: make test

- name: Test with doctest
41 changes: 41 additions & 0 deletions .github/workflows/docs-no-trigger.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
name: Docs

on:
pull_request:
branches: [ master ]

jobs:
build-doc:
runs-on: [self-hosted, linux, gpu]
env:
ORT_ROOT: '/opt/onnxruntime'

steps:
- uses: actions/checkout@v2
with:
fetch-depth: 0
submodules: 'recursive'

- name: Install dependencies
env:
UPDATE_PIP: 'true'
run: |
rm -rf .dacecache tests/.dacecache
. /opt/setupenv
make clean install

- name: Build docs
run: make doc
env:
DACEML_DOC_BUILD_FPGA: 'True'
DACE_compiler_fpga_vendor: intel_fpga
DACE_compiler_use_cache: 0
DACE_compiler_default_data_types: C
DACE_compiler_intel_fpga_mode: emulator
DACE_optimizer_transform_on_call: 0
DACE_optimizer_autooptimize: 0

- uses: actions/upload-artifact@v2
with:
name: auto_examples_${{ github.sha }}
path: doc/auto_examples/
1 change: 1 addition & 0 deletions .github/workflows/docs.yml
Original file line number Diff line number Diff line change
@@ -27,6 +27,7 @@ jobs:
- name: Build docs
run: make doc
env:
DACEML_DOC_BUILD_FPGA: 'True'
DACEML_DOC_BUILD_CUDA: 'True'

- uses: actions/upload-artifact@v2
41 changes: 41 additions & 0 deletions .github/workflows/fpga-ci.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
name: FPGA CI

on:
push:
branches: [ master ]
pull_request:
branches: [ master ]

jobs:
test-fpga:
runs-on: [self-hosted, linux, intel-fpga]
env:
ORT_ROOT: '/opt/onnxruntime'

steps:
- uses: actions/checkout@v2
with:
fetch-depth: 0
submodules: 'recursive'

- name: Install dependencies
env:
UPDATE_PIP: 'true'
run: |
rm -rf .dacecache tests/.dacecache
. /opt/setupenv
make clean install

- name: Run Intel FPGA tests
env:
PYTEST_ARGS: --cov=daceml --cov-report=term --cov-report xml --cov-config=.coveragerc -s -m "not slow and fpga"
DACE_compiler_fpga_vendor: intel_fpga
DACE_compiler_use_cache: 0
DACE_compiler_default_data_types: C
DACE_compiler_intel_fpga_mode: emulator
DACE_optimizer_transform_on_call: 0
DACE_optimizer_autooptimize: 0
run: make test-intel-fpga

- name: Upload coverage
run: make codecov
2 changes: 1 addition & 1 deletion .github/workflows/gpu-ci.yml
Original file line number Diff line number Diff line change
@@ -28,7 +28,7 @@ jobs:

- name: Test with pytest
env:
PYTEST_ARGS: --cov=daceml --cov-report=term --cov-report xml --cov-config=.coveragerc --gpu-only -m "not slow"
PYTEST_ARGS: --cov=daceml --cov-report=term --cov-report xml --cov-config=.coveragerc --gpu-only -m "not slow and not fpga"
run: make test

- name: Upload coverage
4 changes: 4 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
VENV_PATH ?= venv
PYTHON ?= python
PYTHON_BINARY ?= python
PYTEST ?= pytest
PIP ?= pip
YAPF ?= yapf
@@ -53,6 +54,9 @@ test-parallel:
test-gpu:
$(ACTIVATE) $(PYTEST) $(PYTEST_ARGS) tests --gpu

test-intel-fpga:
$(ACTIVATE) $(PYTEST) $(PYTEST_ARGS) tests/pytorch/fpga/

codecov:
curl -s https://codecov.io/bash | bash

11 changes: 8 additions & 3 deletions daceml/autodiff/backward_pass_generator.py
Original file line number Diff line number Diff line change
@@ -382,8 +382,13 @@ def _expand_nodes(self, subgraph: dstate.StateSubgraphView) -> bool:

# only check others if we didn't break out of the above loop
if isinstance(node, ONNXOp):
for impl in ONNXForward.registered_implementations(
node.schema.name):
impls = ONNXForward.registered_implementations(
node.schema.name)

# order the implementations so that implementations containing "pure" are tried first
impls = [i for name, i in impls if "pure" in name
] + [i for name, i in impls if "pure" not in name]
for impl in impls:
if impl.forward_can_be_applied(node, state, self.sdfg):
# try to apply the expansion
class Expansion(xf.ExpandTransformation):
@@ -403,7 +408,7 @@ def annotates_memlets() -> bool:
verify=False,
_match_node=node)
expanded_something = True
continue
break

# This could later on be changed to check if the expansion is differentiable and if not, move
# on to the next expansion. For now we will just apply the first one that matches, prioritizing ones that
2 changes: 1 addition & 1 deletion daceml/onnx/binary_utilities/op_checker.py
Original file line number Diff line number Diff line change
@@ -21,7 +21,7 @@ def check_op(sdfg, state, node, cuda=False) -> Tuple[List[bool], List[bool]]:
log.debug(f"Checking node {node}")

with ORTCAPIInterface() as api,\
KernelSession(api) as session,\
KernelSession(api, cuda=cuda) as session,\
ExecutableKernelContext(api, session, node.name, node.schema.name) as context:

for attribute, onnx_attribute in node.schema.attributes.items():
11 changes: 7 additions & 4 deletions daceml/onnx/forward_implementation_abc.py
Original file line number Diff line number Diff line change
@@ -39,12 +39,15 @@ def forward(node: ONNXOp, state: SDFGState,
"""
...

@staticmethod
def registered_implementations(op_name: str) -> typing.List["ONNXForward"]:
@classmethod
def registered_implementations(
cls,
op_name: str) -> typing.List[typing.Tuple[str, "ONNXForward"]]:
impls = []
for impl, args in ONNXForward.extensions().items():
for impl, args in cls.extensions().items():
if "op" in args and args["op"] == op_name:
impls.append(impl)
impls.append((args["name"], impl))

return impls


10 changes: 6 additions & 4 deletions daceml/onnx/nodes/onnx_op.py
Original file line number Diff line number Diff line change
@@ -376,11 +376,13 @@ def validate(self, sdfg: SDFG, state: SDFGState):

edge_data = edge.data.data
edge_dtype = sdfg.arrays[edge_data].dtype
# edge_dtype can be a vector type
if matched.param_type == ONNXParameterType.Variadic and not matched.homogeneous:
# non homogeneous parameters don't need to be consistent
pass
elif matched.type_str in assigned_params and assigned_params[
matched.type_str] != edge_dtype:
elif matched.type_str in assigned_params and (
assigned_params[matched.type_str] != edge_dtype and
assigned_params[matched.type_str] != edge_dtype.base_type):
raise ValueError(
"Could not solve type constraints;"
" excepted type '{expected}' for {param_type} '{conn_name}', got type '{actual}'"
@@ -391,14 +393,14 @@ def validate(self, sdfg: SDFG, state: SDFGState):

# otherwise, matched.type_str was not assigned a type yet: try to assign it
cons = self.schema.type_constraints[matched.type_str]
if edge_dtype not in cons.types:
if edge_dtype not in cons.types and edge_dtype.base_type not in cons.types:
raise ValueError(
"Expected type in '{possible}' for {param_type} '{conn_name}', got type '{actual}'"
.format(possible=cons.types,
param_type="input" if is_input else "output",
conn_name=matched.name,
actual=edge_dtype))
assigned_params[matched.type_str] = edge_dtype
assigned_params[matched.type_str] = edge_dtype.base_type

# check that we have all required attributes
##########################################
1 change: 1 addition & 0 deletions daceml/onnx/op_implementations/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from .utils import *
from .pure_implementations import *
from .fpga_implementations import *
from .img_op_implementations import *
from .cudnn_implementations import *
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