Update StarFive U-Boot to work with upstream OpenSBI generic platform #17
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… ONLY)" This reverts commit 1b36682. The SiFive CLINT driver is supposed to work in M-mode only. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
As we are running in S-mode, RISCV_TIMER has to be used. Adjust the config file accordingly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This was referenced Jun 2, 2021
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I've installed upstream OpenSBI and this (built by @atishp04) on my board and so far I haven't seen the issue in starfive-tech/linux#15 even though OpenSBI has choosen both hart 0 and hart 1 as boot hart. @lbmeng Thanks! |
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@tekkamanninja can we merge this? |
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I seem to have the privilege to click the button so if everyone agrees, I can do the merge. |
esmil
referenced
this pull request
in starfive-tech/linux
Aug 11, 2021
This adds a combined pinctrl and gpio driver for the StarFive Ltd. JH7100 RISC-V SoC [1]. For each "GPIO" there are two registers for configuring the output and output enable signals, which may come from other peripherals, and controlling the GPIOs from software amounts to setting these signals to constant 0 or constant 1. In other words the same registers are used for both pinmuxing and controlling the GPIOs, which makes it easier to combine the pinctrl and gpio driver in one. The gpio code is adapted from the gpio driver in the vendor tree written by Huan Feng with cleanups and fixes by Drew and me. [1] https://github.com/starfive-tech/beaglev_doc Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Drew Fustini <drew@beagleboard.org>
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This addresses starfive-tech/opensbi#4
Tested with: