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Update StarFive U-Boot to work with upstream OpenSBI generic platform #17

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merged 2 commits into from
Jun 3, 2021
Merged

Update StarFive U-Boot to work with upstream OpenSBI generic platform #17

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977abc5
Revert "riscv: Enable the SiFive CLINT block driver in S-Mode(VIC7100…
lbmeng Jun 2, 2021
2feaab2
starfive: beaglev: Disable SIFIVE_CLINT and enable RISCV_TIMER
lbmeng Jun 2, 2021
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3 changes: 2 additions & 1 deletion arch/riscv/Kconfig
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Expand Up @@ -175,7 +175,8 @@ config DMA_ADDR_T_64BIT
default y if 64BIT

config SIFIVE_CLINT
bool "Enable the SiFive CLINT block driver"
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
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1 change: 0 additions & 1 deletion board/starfive/vic7100/Kconfig
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Expand Up @@ -63,6 +63,5 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SYSRESET
imply SYSRESET_GPIO
imply CMD_DHCP
imply SIFIVE_CLINT

endif
3 changes: 1 addition & 2 deletions configs/starfive_vic7100_beagle_v_smode_defconfig
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Expand Up @@ -84,7 +84,6 @@ CONFIG_CMODEL_MEDLOW=y
CONFIG_RISCV_SMODE=y
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_ISA_A=y
CONFIG_SIFIVE_CLINT=y
CONFIG_SBI=y
# CONFIG_SBI_V01 is not set
CONFIG_SBI_V02=y
Expand Down Expand Up @@ -1121,7 +1120,7 @@ CONFIG_TIMER=y
# CONFIG_RENESAS_OSTM_TIMER is not set
# CONFIG_NOMADIK_MTU_TIMER is not set
# CONFIG_OMAP_TIMER is not set
# CONFIG_RISCV_TIMER is not set
CONFIG_RISCV_TIMER=y
# CONFIG_ROCKCHIP_TIMER is not set
# CONFIG_STI_TIMER is not set
# CONFIG_STM32_TIMER is not set
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