soc: arm: xilinx_zynqmp: Use CMSIS-Core(R).

This commit updates the 'xilinx_zynqmp' SoC initialisation code to use the preliminary CMSIS-Core(R) implementation added in the PR zephyrproject-rtos#19964. In addition, it also defines the Core IP revision value for the SoC as specified in the Zynq UltraScale+ Device Technical Reference Manual. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
stephanosio · Nov 5, 2019 · 6ac68f5 · 6ac68f5
1 parent b90436d
commit 6ac68f5
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Showing 2 changed files with 7 additions and 9 deletions.
diff --git a/soc/arm/xilinx_zynqmp/soc.c b/soc/arm/xilinx_zynqmp/soc.c
@@ -9,6 +9,8 @@
 #include <device.h>
 #include <init.h>
 
+#include <arch/arm/cortex_r/cmsis.h>
+
 /**
  *
  * @brief Perform basic hardware initialization
@@ -31,9 +33,7 @@ SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 
 void z_platform_init(void)
 {
-	__asm__ volatile(
-		"mrc p15, 0, r0, c1, c0, 0;"		/* SCTLR */
-		"bic r0, r0, #" TOSTR(HIVECS) ";"	/* Vector table at 0 */
-		"mcr p15, 0, r0, c1, c0, 0;"
-		: : : "memory");
+	unsigned int sctlr = __get_SCTLR();
+	sctlr &= ~SCTLR_V_Msk;
+	__set_SCTLR(sctlr);
 }
diff --git a/soc/arm/xilinx_zynqmp/soc.h b/soc/arm/xilinx_zynqmp/soc.h
@@ -8,12 +8,10 @@
 #ifndef _BOARD__H_
 #define _BOARD__H_
 
-#include <misc/util.h>
-
 #ifndef _ASMLANGUAGE
 
-#include <device.h>
-#include <misc/util.h>
+/* Define CMSIS configurations */
+#define __CR_REV                1U
 
 #endif /* !_ASMLANGUAGE */