Merge pull request #260 from visitorckw/full-F-extension-support

Comprehensive F extension support with SoftFloat integration

.ci/riscv-tests.sh

@@ -15,3 +15,4 @@ make arch-test RISCV_DEVICE=IM  || exit 1
 make arch-test RISCV_DEVICE=IC || exit 1
 make arch-test RISCV_DEVICE=IZifencei || exit 1
 make arch-test RISCV_DEVICE=IZicsr || exit 1
+make arch-test RISCV_DEVICE=FZicsr || exit 1

.gitignore

@@ -12,6 +12,7 @@ build/.config
 build/rv32emu
 build/arch-test
 build/mini-gdbstub
+build/softfloat
 build/cache/
 build/map/
 *.o

.gitmodules

@@ -4,3 +4,6 @@
 [submodule "mini-gdbstub"]
 	path = src/mini-gdbstub
 	url = https://github.com/RinHizakura/mini-gdbstub
+[submodule "softfloat"]
+	path = src/softfloat
+	url = https://github.com/visitorckw/berkeley-softfloat-3

Makefile

@@ -64,6 +64,14 @@ $(call set-feature, EXT_C)
 ENABLE_EXT_F ?= 1
 $(call set-feature, EXT_F)
 ifeq ($(call has, EXT_F), 1)
+SOFTFLOAT_OUT = $(abspath $(OUT)/softfloat)
+src/softfloat/build/Linux-RISCV-GCC/Makefile:
+	git submodule update --init src/softfloat/
+SOFTFLOAT_LIB := $(SOFTFLOAT_OUT)/softfloat.a
+$(SOFTFLOAT_LIB): src/softfloat/build/Linux-RISCV-GCC/Makefile
+	$(MAKE) -C $(dir $<) BUILD_DIR=$(SOFTFLOAT_OUT)
+$(OUT)/decode.o $(OUT)/riscv.o: $(SOFTFLOAT_LIB)
+LDFLAGS += $(SOFTFLOAT_LIB)
 LDFLAGS += -lm
 endif
 
@@ -211,5 +219,6 @@ distclean: clean
 	$(RM) *.zip
 	$(RM) -r $(OUT)/mini-gdbstub
 	-$(RM) $(OUT)/.config
+	-$(RM) -r $(OUT)/softfloat
 
 -include $(deps)

README.md

@@ -24,8 +24,7 @@ a focus on efficiency and readability.
 
 Features:
 * Fast interpreter for executing the RV32 ISA
-* Comprehensive support for RV32I and M, A, C extensions
-* Partial support for the F extension
+* Comprehensive support for RV32I and M, A, C, F extensions
 * Memory-efficient design
 * Built-in ELF loader
 * Implementation of commonly used newlib system calls
@@ -143,7 +142,6 @@ Current progress of this emulator in riscv-arch-test (RV32):
     - `C`: Standard Extension for Compressed Instruction
     - `Zifencei`: Instruction-Fetch Fence
     - `privilege`: RISCV Privileged Specification
-* Unsupported tests (runnable but incomplete)
     - `F` Standard Extension for Single-Precision Floating-Point
 
 Detail in riscv-arch-test:

src/riscv.c

@@ -267,7 +267,8 @@ void rv_reset(riscv_t *rv, riscv_word_t pc, int argc, char **args)
 #if RV32_HAS(EXT_F)
     rv->csr_misa |= MISA_F;
     /* reset float registers */
-    memset(rv->F, 0, sizeof(float) * N_RV_REGS);
+    for (int i = 0; i < N_RV_REGS; i++)
+        rv->F[i].v = 0;
     rv->csr_fcsr = 0;
 #endif
 

src/riscv.h

@@ -6,6 +6,9 @@
 #pragma once
 #include <stdbool.h>
 #include <stdint.h>
+#if RV32_HAS(EXT_F)
+#include "softfloat/softfloat.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -89,7 +92,9 @@ typedef uint32_t riscv_word_t;
 typedef uint16_t riscv_half_t;
 typedef uint8_t riscv_byte_t;
 typedef uint32_t riscv_exception_t;
-typedef float riscv_float_t;
+#if RV32_HAS(EXT_F)
+typedef float32_t riscv_float_t;
+#endif
 
 /* memory read handlers */
 typedef riscv_word_t (*riscv_mem_ifetch)(riscv_word_t addr);

src/riscv_private.h

@@ -99,10 +99,7 @@ struct riscv_internal {
 
 #if RV32_HAS(EXT_F)
     /* float registers */
-    union {
-        riscv_float_t F[N_RV_REGS];
-        uint32_t F_int[N_RV_REGS]; /* integer shortcut */
-    };
+    riscv_float_t F[N_RV_REGS];
     uint32_t csr_fcsr;
 #endif