cmp pins fix + chisel 3 update

[tjarker]

• fix cmp pins by making field io not a concrete member of CmpDevice blue print
• update cmp and argo wrapper modules to chisel 3
• fix async component black boxes and move related verilog files into the verilog folder
  • both files are now copied into the build folder when generating verilog for patmos
• fix verilator complaining about multi-driven signals in Argo dual-port memories by setting global flag -Wno-MULTIDRIVEN

[tjarker]

I ran some of the cmp programs on patemu and it seems to work. I have problems with my setup right now to be able to test something on the actual FPGA.

[torurstrom]

Looks good. The next step is to test it on actual hardware, but as that was already broken there is no reason to delay the multicore emulator fix.