cmp pins fix + chisel 3 update

Makefile

@@ -113,7 +113,7 @@ CORECNTT:=$(shell lscpu | grep 'Core(s) per socket:')
 emulator:
 	-mkdir -p $(HWBUILDDIR)
 	$(MAKE) -C hardware verilog BOOTAPP=$(BOOTAPP) BOARD=$(BOARD)
-	-cd $(HWBUILDDIR) && verilator --cc ../harnessConfig.vlt Patmos.v --top-module Patmos +define+TOP_TYPE=VPatmos --threads 1 -CFLAGS "-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VPatmos -DVL_USER_FINISH -include VPatmos.h" -Mdir $(HWBUILDDIR) --exe ../Patmos-harness.cpp -LDFLAGS -lelf --trace-fst
+	-cd $(HWBUILDDIR) && verilator --cc ../harnessConfig.vlt Patmos.v --top-module Patmos +define+TOP_TYPE=VPatmos --threads 1 -CFLAGS "-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VPatmos -DVL_USER_FINISH -include VPatmos.h" -Wno-MULTIDRIVEN -Mdir $(HWBUILDDIR) --exe ../Patmos-harness.cpp -LDFLAGS -lelf --trace-fst
 	-cd $(HWBUILDDIR) && make -j -f VPatmos.mk
 	-cp $(HWBUILDDIR)/VPatmos $(HWBUILDDIR)/emulator
 	-mkdir -p $(HWINSTALLDIR)/bin

hardware/Makefile

@@ -97,6 +97,8 @@ view:
 verilog: $(HWBUILDDIR)/$(HWMODULEPREFIX)Patmos.v
 	cd ../../argo && sbt "runMain argo.Argo"
 	cp ../../argo/argo_build/*.v $(HWBUILDDIR)
+	cp verilog/AsyncArbiter.v $(HWBUILDDIR)
+	cp verilog/AsyncMutex.v $(HWBUILDDIR)
 
 modules: \
 	$(HWBUILDDIR)/$(HWMODULEPREFIX)PatmosCore.v \

hardware/src/main/scala/argo/Argo.scala

@@ -24,7 +24,7 @@ class CmpArgoIO(corecnt : Int, val argoConf: ArgoConfig) extends CmpIO(corecnt :
   override val cores = Vec(corecnt, new OcpArgoSlavePort(ADDR_WIDTH, DATA_WIDTH, argoConf)).asInstanceOf[Vec[OcpCoreSlavePort]]
 }
 
-class Argo(nrCores: Int, wrapped: Boolean = false, emulateBB: Boolean = false) extends Module {
+class Argo(nrCores: Int, wrapped: Boolean = false, emulateBB: Boolean = false) extends CmpDevice(nrCores) {
   ArgoConfig.setCores(nrCores)
   val argoConf = ArgoConfig.getConfig
   val io = IO(new CmpArgoIO(argoConf.CORES, argoConf))

hardware/src/main/scala/argo/ArgoNoC.scala

@@ -28,6 +28,19 @@ class ArgoNoC(val argoConf: ArgoConfig, wrapped: Boolean = false, emulateBB: Boo
     val argoNodes = (0 until argoConf.M).map(j =>
       (0 until argoConf.N).map(i =>
         if (emulateBB) Module(new NoCNodeDummy(argoConf, i == 0 && j == 0)) else Module(new NoCNodeWrapper(argoConf, i == 0 && j == 0))))
+
+    if (!emulateBB) {
+      argoNodes.flatten.foreach(n => {
+        val node = n.asInstanceOf[NoCNodeWrapper]
+        Seq(node.io.north_in, node.io.east_in, node.io.south_in, node.io.west_in).foreach(p => {
+          p.f.req := false.B
+        })
+        Seq(node.io.north_out, node.io.east_out, node.io.south_out, node.io.west_out).foreach(p => {
+          p.b.ack := false.B
+        })
+      })
+    }
+
     val argoMesh = Wire(Vec(argoConf.M, Vec(argoConf.N, new NodeInterconnection(argoConf))))
     /*
     * Nodes Port Interconnect

hardware/src/main/scala/argo/NoCNodeWrapper.scala

@@ -44,7 +44,7 @@ class NoCNodeDummy(val argoConf: ArgoConfig, master: Boolean) extends Module {
   val respReg = RegInit(OcpResp.NULL)
   val acceptReg = RegInit(false.B)
 
-  acceptReg := (io.proc.M.Cmd === OcpCmd.WR) && ~acceptReg
+  acceptReg := (io.proc.M.Cmd === OcpCmd.WR) && !acceptReg
 
   when (io.proc.M.Cmd===OcpCmd.WR && acceptReg) {
     when(io.proc.M.Addr(15, 12) === 0.U){

hardware/src/main/scala/cmp/AsyncArbiterTree.scala

@@ -7,7 +7,8 @@
  */
 package cmp
 
-import Chisel._
+import chisel3._
+import chisel3.util.HasBlackBoxResource
 
 class AsyncArbiterIO extends Bundle
 {
@@ -19,45 +20,29 @@ class AsyncArbiterIO extends Bundle
 
 class AsyncArbiterTreeIO(cnt: Int) extends AsyncArbiterIO
 {
-  val cores = Vec(cnt, new AsyncArbiterIO().flip)
+  val cores = Vec(cnt, Flipped(new AsyncArbiterIO()))
 
   override def clone = new AsyncArbiterTreeIO(cnt).asInstanceOf[this.type]
 }
 
-class AsyncArbiterBB() extends BlackBox {
-  val io = new AsyncArbiterIO()
-  {
+class AsyncArbiter extends BlackBox {
+  val io = IO(new AsyncArbiterIO() {
     val req1 = Input(Bool())
     val req2 = Input(Bool())
     val ack1 = Output(Bool())
     val ack2 = Output(Bool())
-  }
-  //throw new Error("BlackBox wrapper for AsyncArbiter needs update for Chisel 3")
-
-  // should be commented out to compile for chisel3
-  // rename component
-  /*setModuleName("AsyncArbiter")
-
-  renameClock(clock, "clk")
-  renameReset("rst")
-
-  io.req.setName("req")
-  io.req1.setName("req1")
-  io.req2.setName("req2")
-  io.ack.setName("ack")
-  io.ack1.setName("ack1")
-  io.ack2.setName("ack2")*/
+  })
 }
 
 abstract class AsyncArbiterBase(corecnt: Int) extends Module {
-  val io = new AsyncArbiterTreeIO(corecnt)
+  val io = IO(new AsyncArbiterTreeIO(corecnt))
 }
 
 class AsyncArbiterTree(corecnt : Int) extends AsyncArbiterBase(corecnt) {
 
   val leafarbiters = (0 until math.ceil(corecnt/2).toInt).map(i =>
   {
-    val arbiter = Module(new AsyncArbiterBB())
+    val arbiter = Module(new AsyncArbiter())
     val idx = i*2
     arbiter.io.req1 := io.cores(idx).req
     io.cores(idx).ack := arbiter.io.ack1
@@ -71,8 +56,8 @@ class AsyncArbiterTree(corecnt : Int) extends AsyncArbiterBase(corecnt) {
 
 
 
-  val genarbiter = new ((IndexedSeq[AsyncArbiterBB]) => AsyncArbiterBB){
-    def apply(children:IndexedSeq[AsyncArbiterBB]):AsyncArbiterBB =
+  val genarbiter = new ((IndexedSeq[AsyncArbiter]) => AsyncArbiter){
+    def apply(children:IndexedSeq[AsyncArbiter]):AsyncArbiter =
     {
       val len = children.count(e => true)
       println(len)
@@ -90,7 +75,7 @@ class AsyncArbiterTree(corecnt : Int) extends AsyncArbiterBase(corecnt) {
       val child1 = _children._1
       val child2 = _children._2
 
-      val parent = Module(new AsyncArbiterBB())
+      val parent = Module(new AsyncArbiter())
 
       parent.io.req1 := child1.io.req
       child1.io.ack := parent.io.ack1

hardware/src/main/scala/cmp/AsyncLock.scala

@@ -6,7 +6,8 @@
  */
 package cmp
 
-import Chisel._
+import chisel3._
+import chisel3.util._
 import ocp._
 import patmos.Constants._
 
@@ -22,20 +23,8 @@ class AsyncMutexIO extends Bundle
   override def clone = new AsyncMutexIO().asInstanceOf[this.type]
 }
 
-class AsyncMutexBB() extends BlackBox {
+class AsyncMutex extends BlackBox {
   val io = new AsyncMutexIO()
-  //throw new Error("BlackBox wrapper for AsyncMuteX in AsyncLock.scala needs update for Chisel 3")
-  // rename component
-  // should be Commented out to compile for chisel3
-  /*setModuleName("AsyncMutex")
-
-  renameClock(clock, "clk")
-  renameReset("rst")
-
-  io.req1.setName("req1")
-  io.req2.setName("req2")
-  io.gnt1.setName("gnt1")
-  io.gnt2.setName("gnt2")*/
 }
 
 class AsyncArbiterMesh(corecnt: Int) extends AsyncArbiterBase(corecnt) {
@@ -71,12 +60,11 @@ class AsyncArbiterMesh(corecnt: Int) extends AsyncArbiterBase(corecnt) {
 
     val seq = genset(IndexedSeq(), 1)
 
-    if(seq.isEmpty)
-      throwException("Should not happen!")
+    require(seq.nonEmpty, "Should not happen!")
     for(tup <- seq) {
       avail = avail.filter(e => e != tup)
 
-      val mutex = Module(new AsyncMutexBB())
+      val mutex = Module(new AsyncMutex())
 
       mutex.io.req1 := ins(tup._1)
       ins(tup._1) = mutex.io.gnt1
@@ -94,7 +82,7 @@ class AsyncArbiterMesh(corecnt: Int) extends AsyncArbiterBase(corecnt) {
   }
 }
 
-class AsyncLock(corecnt: Int, lckcnt: Int, fair: Boolean = false) extends Module {
+class AsyncLock(corecnt: Int, lckcnt: Int, fair: Boolean = false) extends CmpDevice(corecnt) {
 
   val arbiters =
     if(!fair)
@@ -105,23 +93,22 @@ class AsyncLock(corecnt: Int, lckcnt: Int, fair: Boolean = false) extends Module
       arb
     })
     else
-      (0 until lckcnt).map(i => Module(new AsyncArbiterMesh(corecnt)))
+      Seq.fill(lckcnt)(Module(new AsyncArbiterMesh(corecnt)))
 
-  val arbiterio = Vec(arbiters.map(e => e.io))
+  val arbiterio = arbiters.map(_.io)
 
   val io = IO(new CmpIO(corecnt)) //Vec(corecnt,new OcpCoreSlavePort(ADDR_WIDTH, DATA_WIDTH))
 
   for (i <- 0 until corecnt) {
 
     val addr = io.cores(i).M.Addr(log2Up(lckcnt)-1+2, 2)
-    val acks = Bits(width = lckcnt)
-    acks := 0.U
-    val blck = acks.orR
+    val acks = WireDefault(VecInit.fill(lckcnt)(false.B))
+    val blck = acks.reduce(_ || _)
 
     for (j <- 0 until lckcnt) {
-      val reqReg = Reg(init = false.B)
+      val reqReg = RegInit(init = false.B)
       arbiterio(j).cores(i).req := reqReg
-      val ackReg = Reg(next = Reg(next = arbiterio(j).cores(i).ack))
+      val ackReg = RegNext(next = RegNext(next = arbiterio(j).cores(i).ack))
       acks(j) := ackReg =/= reqReg
 
       when(addr === j.U) {
@@ -133,7 +120,7 @@ class AsyncLock(corecnt: Int, lckcnt: Int, fair: Boolean = false) extends Module
       }
     }
 
-    val dvaReg = Reg(init = false.B)
+    val dvaReg = RegInit(init = false.B)
 
     when(io.cores(i).M.Cmd =/= OcpCmd.IDLE) {
       dvaReg := true.B

hardware/src/main/scala/cmp/CASPM.scala

@@ -6,30 +6,32 @@
 
 package cmp
 
-import Chisel._
-import chisel3.VecInit
+import chisel3._
+import chisel3.util._
 import ocp._
 import patmos.Constants._
 import patmos._
 
 class CASPM(corecnt: Int, size: Int) extends CmpDevice(corecnt) {
 
+  val io = IO(new CmpIO(corecnt))
+
   val spm = Module(new Spm(size))
 
   val cntmax = 2.U
-  val precnt = Reg(init = 0.U(cntmax.getWidth.W))
+  val precnt = RegInit(init = 0.U(cntmax.getWidth.W))
   precnt := Mux(precnt === cntmax, 0.U, precnt + 1.U)
-  val cnt = Reg(init = 0.U(log2Up(corecnt).W))
+  val cnt = RegInit(init = 0.U(log2Up(corecnt).W))
   cnt := Mux(precnt =/= cntmax, cnt, Mux(cnt === (corecnt-1).U, 0.U, cnt + 1.U))
 
   val cmdRegs = RegInit(VecInit(Seq.fill(corecnt)(OcpCmd.RD)))
-  val addrRegs = Reg(Vec(corecnt, spm.io.M.Addr))
-  val newvalRegs = Reg(Vec(corecnt, spm.io.M.Data))
-  val bytenRegs = Reg(Vec(corecnt, spm.io.M.ByteEn))
+  val addrRegs = Reg(Vec(corecnt, chiselTypeOf(spm.io.M.Addr)))
+  val newvalRegs = Reg(Vec(corecnt, chiselTypeOf(spm.io.M.Data)))
+  val bytenRegs = Reg(Vec(corecnt, chiselTypeOf(spm.io.M.ByteEn)))
 
-  val expvalRegs = Reg(Vec(corecnt, spm.io.S.Data))
+  val expvalRegs = Reg(Vec(corecnt, chiselTypeOf(spm.io.S.Data)))
 
-  val sIdle :: sRead :: sWrite :: Nil = Enum(UInt(),3)
+  val sIdle :: sRead :: sWrite :: Nil = Enum(3)
   val states = RegInit(VecInit(Seq.fill(corecnt)(sIdle)))
 
   spm.io.M.Cmd := cmdRegs(cnt)
@@ -39,7 +41,7 @@ class CASPM(corecnt: Int, size: Int) extends CmpDevice(corecnt) {
 
   for (i <- 0 until corecnt) {
 
-    val respReg = Reg(io.cores(i).S.Resp, OcpResp.NULL)
+    val respReg = Reg(chiselTypeOf(io.cores(i).S.Resp))
     io.cores(i).S.Resp := respReg
     io.cores(i).S.Data := spm.io.S.Data
 

hardware/src/main/scala/cmp/CmpDevice.scala

@@ -8,5 +8,5 @@ import chisel3._
   * @param cnt
   */
 abstract class CmpDevice(cnt: Int) extends Module {
-  val io = IO(new CmpIO(cnt))
+  val io: CmpIO
 }

hardware/src/main/scala/cmp/CmpIO.scala

@@ -4,11 +4,6 @@ import chisel3._
 import ocp.OcpCoreSlavePort
 import patmos.Constants.{ADDR_WIDTH, DATA_WIDTH}
 
-class CmpIO(val corecnt: Int) extends Bundle with patmos.HasPins {
+class CmpIO(val corecnt: Int) extends Bundle {
   val cores = Vec(corecnt, new OcpCoreSlavePort(ADDR_WIDTH, DATA_WIDTH))
-  // TODO: just for now to move to Chisel 3.5, needs a btter fix in the future
-  override val pins = new Bundle {
-    val tx = Output(Bits(1.W))
-    val rx = Input(Bits(1.W))
-  }
 }

hardware/src/main/scala/cmp/Hardlock.scala

@@ -9,8 +9,8 @@
  */
 package cmp
 
-import Chisel._
-import chisel3.VecInit
+import chisel3._
+import chisel3.util._
 import patmos.Constants._
 import ocp._
 
@@ -75,15 +75,14 @@ class Hardlock(coreCnt : Int,lckCnt : Int) extends AbstractHardlock(coreCnt, lck
 }
 
 class HardlockOCPWrapper(nrCores: Int, hardlockgen: () => AbstractHardlock) extends CmpDevice(nrCores) {
+  val io = IO(new CmpIO(nrCores))
+
 
   val hardlock = Module(hardlockgen())
 
-  // TODO: workaround:
-  io.pins.tx := 0.U
-
   // Mapping between internal io and OCP here
 
-  val reqReg = Reg(init = Bits(0,hardlock.CoreCount))
+  val reqReg = RegInit(init = 0.U(hardlock.CoreCount.W))
   val reqBools = Wire(Vec(hardlock.CoreCount, Bool()))
 
   reqBools := reqReg.asBools
@@ -98,11 +97,11 @@ class HardlockOCPWrapper(nrCores: Int, hardlockgen: () => AbstractHardlock) exte
 
     when(io.cores(i).M.Cmd =/= OcpCmd.IDLE) {
       reqBools(i) := true.B
-      reqReg := reqBools.asUInt()
+      reqReg := reqBools.asUInt
     }
     .elsewhen(reqReg(i) === true.B && hardlock.io.cores(i).blck === false.B) {
       reqBools(i) := false.B
-      reqReg := reqBools.asUInt()
+      reqReg := reqBools.asUInt
     }
 
     io.cores(i).S.Resp := OcpResp.NULL

hardware/src/main/scala/cmp/LedsCmp.scala

@@ -1,36 +1,33 @@
-/*
 
 package cmp
 
-import Chisel._
+import chisel3._
 import io._
 import ocp.OcpCoreSlavePort
 import patmos.Constants.{ADDR_WIDTH, DATA_WIDTH}
 
 
-MS: commented out for the moment until we find a good better solution for pins on CPM devices.
-
-class LedsCmp(nrCores: Int, nrLedPerCore: Int) extends Module {
-  val io = new CmpIO(nrCores) with patmos.HasPins {
+class LedsCmp(nrCores: Int, nrLedPerCore: Int) extends CmpDevice(nrCores) {
+  val io = IO(new CmpIO(nrCores) with patmos.HasPins {
     override val pins = new Bundle() {
-      val led = Output(Bits(width = nrCores * nrLedPerCore))
+      val led = Output(UInt((nrCores * nrLedPerCore).W))
     }
-  }
+  })
   // commented out below as chisel3 do not support setWidth, trait are parameterless which means 
   // there is no good way of setting with. All uses of this class has nrLedPerCore = 1 anyway 
   //io.ledsCmpPins.led.setWidth(nrCores * nrLedPerCore) //modify number of ledPins dynamically
 
   io.pins.led := 0.U
 
-  val ledDevs = Vec(nrCores, Module(new Leds(nrLedPerCore)).io)
+  val ledDevs = Seq.fill(nrCores)(Module(new Leds(nrLedPerCore)).io)
 
   //Wire one led IO device per core, each with a number of led
   for (i <- 0 until nrCores) {
     ledDevs(i).ocp.M := io.cores(i).M
     io.cores(i).S := ledDevs(i).ocp.S
-    io.pins.led(i) := ledDevs(i).pins.led(0)
+    ledDevs(i).superMode := false.B
   }
+  io.pins.led := ledDevs.map(_.pins.led).reduceLeft((l, h) => h ## l)
 
 }
 
- */