Merge pull request #106 from cr1901/picorv32-data

Updating submodules.
timvideos · Nov 21, 2018 · a3aa096 · a3aa096
2 parents a1b31be + d7168f6
commit a3aa096
Show file tree

Hide file tree

Showing 5 changed files with 5 additions and 5 deletions.
diff --git a/third_party/litedram b/third_party/litedram
diff --git a/third_party/litepcie b/third_party/litepcie
diff --git a/third_party/litevideo b/third_party/litevideo
diff --git a/third_party/litex b/third_party/litex
diff --git a/third_party/migen b/third_party/migen
+71 −0		examples/sim/glbl.v
+703 −0		examples/sim/micron/1024Mb_ddr3_parameters.vh
+691 −0		examples/sim/micron/2048Mb_ddr3_parameters.vh
+691 −0		examples/sim/micron/4096Mb_ddr3_parameters.vh
+526 −0		examples/sim/micron/8192Mb_ddr3_parameters.vh
+2,960 −0		examples/sim/micron/ddr3.v
+232 −0		examples/sim/micron/ddr3_dimm.v
+126 −0		examples/sim/micron/ddr3_mcp.v
+432 −0		examples/sim/micron/ddr3_module.v
+190 −0		examples/sim/micron/readme.txt
+368 −0		examples/sim/micron/subtest.vh
+582 −0		examples/sim/micron/tb.v
+241 −0		examples/sim/sim.py
+33 −0		examples/sim/sim_config.py
+14 −3		litex/boards/platforms/avalanche.py
+0 −64		litex/boards/platforms/sim.py
+1 −0		litex/build/microsemi/__init__.py
+24 −0		litex/build/microsemi/common.py
+241 −0		litex/build/microsemi/libero_soc.py
+36 −0		litex/build/microsemi/platform.py
+22 −23		litex/build/sim/core/sim.c
+18 −3		litex/build/sim/verilator.py
+2 −0		litex/soc/integration/soc_core.py
+57 −0		litex/soc/interconnect/stream.py
+14 −0		litex/soc/software/libbase/crt0-picorv32.S
+0 −1		litex/soc/tools/remote/__init__.py
+60 −0		litex/utils/litex_read_verilog.py
+2 −0		litex/utils/litex_server.py
+66 −3		litex/utils/litex_sim.py
+1 −1		litex/utils/litex_term.py
+4 −3		setup.py
+0 −69		test/test_bitslip.py
+38 −26		test/test_gearbox.py
+12 −2		test/test_targets.py
+50 −11		migen/build/lattice/diamond.py
+2 −2		migen/build/lattice/icestorm.py
+6 −3		migen/build/tools.py