Updating submodules. #106
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Updating submodules. #106
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cr1901
commented
Nov 21, 2018
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cr1901
commented
* litedram changed from 30d9a3e to bc6a3f2
* bc6a3f2 - examples/sim/sim/py: remove apb interface <Florent Kermarrec>
* e7e4bc5 - examples/sim: add ddr3 micron model <Florent Kermarrec>
* f219693 - examples: add simulation <Florent Kermarrec>
* litepcie changed from 48f662e to dddd3b1
* dddd3b1 - phy/s7pciephy: fix soft reset by reseting pcie on cd reset <Florent Kermarrec>
* litevideo changed from 13d85a1 to 0993a4e
* 0993a4e - Merge pull request timvideos#21 from felixheld/licensefix <Tim Ansell>
* d8287db - LICENSE: use right project name <Felix Held>
* litex changed from bc173380 to ab799f7b
* ab799f7b - Merge pull request timvideos#127 from cr1901/picorv32-data <Tim Ansell>
|\
| * 89c70218 - libbase/crt0-picorv32: Add support for .data sections. <William D. Jones>
|/
* 80bdae0e - build/sim/verilator: add trace parameter to enable tracer <Florent Kermarrec>
* 7359a99b - soc_core: convert cpu_type="None" string to None <Florent Kermarrec>
* 5805d630 - build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route <Florent Kermarrec>
* 85f76662 - build/microsemi/common: add async reset synchronizer (using DFN1P0) <Florent Kermarrec>
* e3c6bd58 - build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools <Florent Kermarrec>
* 4c966114 - build/microsemi/libero_soc: add timing constraints support <Florent Kermarrec>
* 60faae49 - boards/platforms/avalanche: fix swapped serial pins <Florent Kermarrec>
* 52396add - boards/platforms/avalanche: rename rst to rst_n (active low reset) <Florent Kermarrec>
* 8e07e1a0 - build/microsemi/libero_soc: associate .pdc to place and route tool. <Florent Kermarrec>
* 5137c2bf - test/test_targets: update <Florent Kermarrec>
* a5ed42ec - soc/interconnect/stream: add Gearbox <Florent Kermarrec>
* 11d536dc - test: remove test_bitslip (integrated in migen) <Florent Kermarrec>
* a25645af - utils: add litex_read_verilog utility <Florent Kermarrec>
* a538d362 - create utils directory and move the litex utils to it <Florent Kermarrec>
* 45ec78e9 - build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board. <Florent Kermarrec>
* 4cb6583b - build: add microsemi template for polarfire fpgas support <Florent Kermarrec>
* migen changed from 0.6.dev-209-gc285c12 to 0.6.dev-211-g022721a
* 022721a - lattice/diamond: Support sourcing by default. <William D. Jones>
* 17e6d34 - fix yosys commands for build_names other than 'top' <Erin Moon>
Full submodule status
--
5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
bc6a3f220a16fbc1208cc23ab5cf072d2b81f62e litedram (remotes/origin/HEAD)
52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
dddd3b16edfc9b345526f4106954b2c6b6f00933 litepcie (remotes/origin/HEAD)
b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (remotes/origin/HEAD)
ab799f7bd7e0ad2063747dc6636de61225e648c4 litex (remotes/origin/HEAD)
022721a81d274a08ccb1b1f7919d4940cce99a73 migen (0.6.dev-211-g022721a)
CarlFK
pushed a commit
to CarlFK/litex-buildenv
that referenced
this pull request
Dec 15, 2018
* litex changed from v0.1-451-g537b0e90 to v0.1-494-g6e327cda
* 6e327cda - bios/sdram: rewrite write_leveling (simplify and improve robustness) <Florent Kermarrec>
* 975be668 - platforms/genesys2: add eth clock timing constraint <Florent Kermarrec>
* 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec>
* 9097573e - Merge pull request timvideos#109 from cr1901/xip-improve <enjoy-digital>
|\
| * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones>
| * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones>
| * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones>
* | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec>
* | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec>
* | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec>
* | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec>
* | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec>
* | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec>
* | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec>
* | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec>
* | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec>
|/
* 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec>
* 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec>
* 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec>
* 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec>
* b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec>
* 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec>
* 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec>
* c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec>
* 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec>
* e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec>
* e9ed7370 - ease RemoteClient import <Florent Kermarrec>
* 346dcf94 - Merge pull request timvideos#108 from xobs/use-csr-accessors <enjoy-digital>
|\
| * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross>
| * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross>
* | 1c1d87f8 - Merge pull request timvideos#106 from cr1901/data-crt0 <Tim Ansell>
|\ \
| |/
| * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones>
|/
* 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec>
* 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec>
* cde72603 - targets/sim: generate csr.csv <Florent Kermarrec>
* f62df502 - targets/sim: add rom-init <Florent Kermarrec>
* 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec>
* 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec>
* a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec>
* 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec>
* bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
* 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec>
* badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec>
Full submodule status
--
5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
ea1ac4d6d72ecb9a65fb884857db8ba6851f3230 litedram (heads/master-170-gea1ac4d)
3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (heads/master-27-g3d86844)
3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (heads/master-45-g3e8de2d)
fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (heads/master-20-gfb72044)
686db4f3cd71bade8dd777d112e66797662f5bad litescope (heads/master-32-g686db4f)
0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c)
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