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icebreaker doesn't set port so make firmware-connect fails #100

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mithro opened this issue Nov 13, 2018 · 2 comments
Open

icebreaker doesn't set port so make firmware-connect fails #100

mithro opened this issue Nov 13, 2018 · 2 comments

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@mithro
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mithro commented Nov 13, 2018 

(LX P=icebreaker.minimal F=stub R=master-lbe) tansell@tansell:~/github/timvideos/litex-buildenv$ make firmware-connect
flterm --port= --speed=115200
[FLTERM] Starting...
Unable to open serial port: No such file or directory
CarlFK pushed a commit to CarlFK/litex-buildenv that referenced this issue Dec 15, 2018
@mithro
Updating submodules.
ee455b6 
 * edid-decode changed from b2da151 to 5eeb151
    * 5eeb151 - edid-decode: replace AdobeYCC/RGB by opYCC/RGB <Hans Verkuil>

 * litedram changed from 7a5ac75 to ea1ac4d
    * ea1ac4d - s6ddrphy: Pass missing nranks parameter. <Tim 'mithro' Ansell>
    * e5696ad - frontend/ecc: add enable csr <Florent Kermarrec>
    * e6ef89a - frontend/axi: optimize burst2beat timings <Florent Kermarrec>
    * 6941285 - frontend/ecc: split Write/Read path and add buffer to improve timings <Florent Kermarrec>
    * 041817d - frontend/ecc: use csr instead of signal for control <Florent Kermarrec>
    * b145b0c - frontend/axi: fix write response implementation <Florent Kermarrec>
    * d23dbf6 - phy: add nranks to all phys <Florent Kermarrec>
    * 461b076 - frontend/ecc: add ecc adapter <Florent Kermarrec>
    * c84b587 - frontend: add initial ecc code (still need to be integrated) <Florent Kermarrec>
    * a8d2672 - phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation <Florent Kermarrec>
    * 5719d71 - phy/s7ddrphy_halfrate_bl8: fix cs_n <Florent Kermarrec>
    * 36fa324 - core/multiplexer: fix regression (introduced by multirank support) <Florent Kermarrec>
    * 42d0e5b - core/multiplexer: add more information on odt fixme <Florent Kermarrec>
    * 919b756 - phy/model: pass nranks to Interface <Florent Kermarrec>
    * f5c7b61 - multirank: set default nranks to 1 if not specified <Florent Kermarrec>
    * f3d403f - s7ddrphy: fix typo (reset_n --> cs_n) <Florent Kermarrec>
    * 37f1dec - multirank: one cs_n/cke/odt/clk per rank <Florent Kermarrec>
    * 3e17d18 - phy: add halfrate_bl8 variant for s7ddrphy <Florent Kermarrec>
    *   412e9a5 - Merge pull request timvideos#38 from enjoy-digital/multirank <enjoy-digital>
    |\
    | * 8ddc6c7 - drive odt of all ranks, fixes and test non regression with 1 rank <Florent Kermarrec>
    | * d4f434d - dfii: send command to all ranks <Florent Kermarrec>
    | * b1c2739 - initial multirank support (nbankmachines = nranks * (2**bankbits)) <Florent Kermarrec>
    * |   d9c2430 - Merge pull request timvideos#36 from JohnSully/timing_1 <enjoy-digital>
    |\ \
    | |/
    |/|
    | * efd7a47 - Fix failing timing <>
    * | cc481be - examples: add sdram_rank_nb and user_ports_id_width <Florent Kermarrec>
    |/
    * 849b1f6 - frontend/axi: generate rlast signal <Florent Kermarrec>
    * 1fa73e4 - test: update <Florent Kermarrec>
    * 7b61b68 - sdram_init: min value for wr is 5 <Florent Kermarrec>
    * 1652ab9 - examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) <Florent Kermarrec>
    * 1e64b7f - examples/litedram_gen: expose resp signals to user <Florent Kermarrec>
    * 700f76c - frontend/axi: add resp signals <Florent Kermarrec>
    * 47fed1b - frontend/axi: add last limitation <Florent Kermarrec>
    * de69867 - examples/litedram_gen: expose last signals to user <Florent Kermarrec>
    * e8bd782 - examples/litedram_gen: expose burst signals to user <Florent Kermarrec>
    * e1598ce - phy/s7ddrphy: fix BL8 assert <Florent Kermarrec>
    * ebba39d - README: update <Florent Kermarrec>
    * e528e92 - phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) <Florent Kermarrec>
    * 6017e7a - phy/s7ddrphy: fix dqs_sys_latency for DDR2 <Florent Kermarrec>
    * 7b42739 - phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions. <Florent Kermarrec>
    * 6148618 - phy/s7ddrphy: use dict in get_cl_cw function <Florent Kermarrec>
    * 5e4dca9 - add examples with standalone cores for arty and genesys2 <Florent Kermarrec>
    * dce4ede - README: update <Florent Kermarrec>
    * f6797a1 - test/test_axi: add burst wrap test and fix code <Florent Kermarrec>
    * 47988d8 - frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification. <Florent Kermarrec>
    * 6cc42c6 - frontend/axi: add wrap burst support <Florent Kermarrec>
    * 9c729ae - core: replace adr with addr on native interface (closer to AXI and allow some simplifications) <Florent Kermarrec>
    * 0506708 - core/controller: remove simulation workaround <Florent Kermarrec>
    * bc8a9ce - README: update <Florent Kermarrec>
    * 6f7ae84 - frontend/axi: increase default depth of buffers to improve performance <Florent Kermarrec>
    * ed7eef1 - phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) <Florent Kermarrec>
    * c37d3af - frontend/bist: only keep random datas (we can generate random addresses with control) <Florent Kermarrec>
    * b1e734b - frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) <Florent Kermarrec>
    * 92c8513 - frontend/axi: add buffer to accept command before converting burst to beats <Florent Kermarrec>
    * c15c474 - test/test_axi: split reads/writes generators <Florent Kermarrec>
    * 95cb7cd - test: rename read/write generators to handlers <Florent Kermarrec>
    * d5d6737 - frontend/axi: fix read id <Florent Kermarrec>
    * 10229d1 - test/test_axi: improve test_axi2native <Florent Kermarrec>
    * 295f016 - frontend/axi: add features/limitations <Florent Kermarrec>
    * 6a46ea3 - test/test_bist: add generator test, remove async test <Florent Kermarrec>
    * 7677a85 - core/bankmachine: expose cmd_buffer_buffered param and small cleanup <Florent Kermarrec>

 * liteeth changed from 24b0d2b to 3d86844
    * 3d86844 - core/mac/sram: fix code refactoring <Florent Kermarrec>
    * 5106bcd - core/mac/sram: simplify last_be code <Florent Kermarrec>
    * ce72e34 - core/mac: pass endianness and use if for last_be gen/check <Florent Kermarrec>
    * 94af3d6 - README: update and rename example_designs to examples <Florent Kermarrec>

 * litepcie changed from a97a691 to 3e8de2d
    * 3e8de2d - phy/s7pciephy: remove clock constraints from phy <Florent Kermarrec>
    * 6f2d97a - README: update and rename example_designs to example <Florent Kermarrec>

 * litesata changed from 002cd25 to fb72044
    * fb72044 - README: update and rename example_designs to examples <Florent Kermarrec>

 * litescope changed from f26e36e to 686db4f
    *   686db4f - Merge pull request timvideos#12 from xobs/default-length <enjoy-digital>
    |\
    | * 4f8b9a3 - analyzer-driver: use default depth from config <Sean Cross>
    |/
    * 7c1c62e - README: update and rename example_designs to examples <Florent Kermarrec>
    * 3567b68 - dump/vcd: fix code generation <Florent Kermarrec>
    * 182b683 - core: change cd parameter to clock_domain (keep retro compatibility for now) <Florent Kermarrec>

 * liteusb changed from e841c56 to 0a9110f
    * 0a9110f - README: update and rename example_designs to examples <Florent Kermarrec>

 * litevideo changed from 7b4240f to 13d85a1
    * 13d85a1 - README: update <Florent Kermarrec>

 * litex changed from 7a14b75c to 537b0e90
    *   537b0e90 - Merge pull request timvideos#101 from cr1901/icestorm-migen-pull <enjoy-digital>
    |\
    | * 5c83c881 - Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. <William D. Jones>
    * | 9c6f76f1 - bios/sdram: mode sdhw() <Florent Kermarrec>
    * | a44bedd5 - bios/sdram: add missing #ifdef <Florent Kermarrec>
    * | 0e68daeb - targets: self.pll_sys --> pll_sys <Florent Kermarrec>
    * | 1468b9f3 - bios/sdram: show all read scans when failing. <Florent Kermarrec>
    * | 07e4c183 - cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) <Florent Kermarrec>
    * | df3f003e - soc_sdram: update with litedram <Florent Kermarrec>
    |/
    *   bebc667d - Merge pull request timvideos#99 from cr1901/mk-copy-main-ram <enjoy-digital>
    |\
    | * bd70ba27 - Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. <William D. Jones>
    * |   69716852 - Merge pull request timvideos#100 from cr1901/tinyprog-fix <enjoy-digital>
    |\ \
    | * | c812321a - lattice/programmer: Use --program-image option with tinyprog if address is given. <William D. Jones>
    | |/
    * | 12a89447 - soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) <Florent Kermarrec>
    * | 2b786065 - targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen <Florent Kermarrec>
    * | 26963d62 - libnet/microudp: (WIP) fix endianness issues <Jean-François Nguyen>
    * |   d9d0320d - Merge pull request timvideos#98 from jfng/fix_typo <enjoy-digital>
    |\ \
    | * | 22c01313 - fix typo and unused include <Jean-François Nguyen>
    |/ /
    * | fb24ac0e - cpu/minerva: add workaround on import until code is released <Florent Kermarrec>
    * | 9cfae4df - setup.py: create litex_sim exec to ease simulation <Florent Kermarrec>
    * | 8f377307 - add Minerva support <Jean-François Nguyen>
    * | 1944289e - litex_server: update pcie and remove bar_size parameter <Florent Kermarrec>
    |/
    *   c5a2d6f3 - Merge pull request timvideos#96 from cr1901/tinyfpga_bx <Tim Ansell>
    |\
    | * 29492624 - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones>
    * |   3cb754da - Merge pull request timvideos#95 from cr1901/lm32-lite <Tim Ansell>
    |\ \
    | * | ed507d61 - Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. <William D. Jones>
    | |/
    * | 28cd2da2 - README: update <Florent Kermarrec>
    |/
    * 05c7b9da - Merge pull request timvideos#94 from cr1901/nextpnr <enjoy-digital>
    * 7af89efc - lattice/icestorm: Add nextpnr pnr as alternate pnr tool. <William D. Jones>

 * migen changed from 0.6.dev-162-ga6082d5 to 0.6.dev-168-gca0df1c
    * ca0df1c - build.platforms: add ice40_up5k_b_evn platform. <whitequark>
    * b2740d9 - build.lattice.icestorm: write build script even on dry run. <whitequark>
    * 2a7e33e - Emit `default_nettype none. <David Craven>
    * cff127d - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones>
    * 97e2651 - kasli: set USERID and USR_ACCESS <Robert Jördens>
    * 58894fb - lattice/icestorm: Add nextpnr as alternate pnr tool. (timvideos#124) <William D. Jones>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 ea1ac4d6d72ecb9a65fb884857db8ba6851f3230 litedram (heads/s6-rank-fix)
 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (remotes/origin/HEAD)
 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (remotes/origin/HEAD)
 fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (remotes/origin/HEAD)
 686db4f3cd71bade8dd777d112e66797662f5bad litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 537b0e9058e6a5b77f434f46f3a56849c82064bd litex (remotes/origin/HEAD)
 ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c)
@ewenmcneill
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Weirdly, I was getting that kind of message on MimasV2 and Arty just now, while trying to test something else; I'm a bit unclear what's changed in the way "make firmware-connect" is handled...

Just mentioning it in case this is not Icebreaker specific.

Ewen

@ewenmcneill
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In #100 (comment) I wrote:

Weirdly, I was getting that kind of message on MimasV2 and Arty just now, while trying to test something else; I'm a bit unclear what's changed in the way "make firmware-connect" is handled...

I figured out how this was happening. My wrapper script for entering environments was unconditionally setting COMM_PORTto the value passed in (for TinyFPGA BX support, where it's not pre-defined), even when no value was passed in. But the Makefiles only set COMM_PORT if it is unset (not if it is empty). So it was not getting set when I ended up with an explicitly empty COMM_PORT value in the environment. When I fix this bit of my wrapper script to conditionally pass in COMM_PORT only if defined, my Mimas v2 (and I'd guess Arty) cases work again for me.

I suspect the Icebreaker and TinyFPGA BX (both of which do not set COMM_PORT) probably need something to catch it being unset and show a more useful error message (eg, export COMM_PORT=....).

Ewen

mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this issue Aug 25, 2020
@mateusz-holenko
Updating submodules.
ddc5f3a 
 * litedram changed from f51052f to 2020.08-3-g5c69da5
    * 5c69da5 - bench: add initial kcu105 bench target. <Florent Kermarrec>
    * 9995c0f - bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. <Florent Kermarrec>
    * ac825e5 - add SPDX License identifier to header and specify file is part of LiteDRAM. <Florent Kermarrec>
    * 198bcba - test/reference: update. <Florent Kermarrec>
    * e3b86fe - getting started: update. <Florent Kermarrec>
    * a0a886e - litedram/init: export xdr ratio and databits. <Florent Kermarrec>
    * 94241d0 - bench: use new platform.request_all on LedChaser. <Florent Kermarrec>
    * 7420597 - bench: add genesys2 bench. <Florent Kermarrec>
    * 37fb44f - add bench directory with a first bench on arty board. <Florent Kermarrec>
    * 4e62d28 - examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards). <Florent Kermarrec>
    * 07bf34d - frontend/wishbone: revert non-FSM version, the FSM one does not seem to cover all cases. <Florent Kermarrec>
    * 9c5ce52 - common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter. <Florent Kermarrec>
    * 06f7192 - frontend/adapter/LiteDRAMNativePortConverter: simplify using ratio. <Florent Kermarrec>
    * a3dfc1d - frontend/adapter: minor cleanups. <Florent Kermarrec>
    * deac4c8 - frontend/adapter: simplify LiteDRAMNativePortDownConverter. <Florent Kermarrec>
    * ce4e7f9 - frontend/adapter: simplify LiteDRAMNativePortCDC using stream.ClockDomainCrossing. <Florent Kermarrec>
    * 16fd46b - frontend: rename adaptation to adapter. <Florent Kermarrec>
    * 4970c8a - frontend/wishbone: simplify/review and get FSM back (ease comprehension). <Florent Kermarrec>
    * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec>
    *   02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital>
    |\
    | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar>
    | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar>
    | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar>
    | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar>
    | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar>
    | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar>
    | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar>
    | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar>
    | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar>
    | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar>
    | * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar>
    | * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar>
    | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar>
    | * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar>
    *   71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital>
    |\
    | * 805a374 - Add support for TDQS mode. <Owen Kirby>
    |/
    * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec>

 * liteeth changed from 792013a to 54acf9f
    * 54acf9f - phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support). <Florent Kermarrec>
    * 64b85e6 - add SPDX License identifier to header and specify file is part or LiteEth. <Florent Kermarrec>
    * f275af8 - liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios. <Florent Kermarrec>
    * 0705b35 - Merge pull request timvideos#46 from Xiretza/gen-py-wishbone <enjoy-digital>
    * 6a9a513 - Update gen.py to work with latest LiteX in wishbone mode <Xiretza>

 * liteiclink changed from 6fdd020 to 2020.08-1-gefd200f
    * efd200f - add SPDX License identifier to header and specify file is part of LiteICLink. <Florent Kermarrec>
    * 60b1994 - getting started: update. <Florent Kermarrec>

 * litepcie changed from 0b6a4bb to 2020.08-1-g0718fd1
    * 0718fd1 - add SPDX License identifier to header and specify file is part of LitePCIe. <Florent Kermarrec>
    * 29d4963 - getting started: update. <Florent Kermarrec>
    * 30456fc - litepcie_gen: add csr_ordering support. <Florent Kermarrec>

 * litesata changed from b36d3a3 to 2020.08-1-gba006a7
    * ba006a7 - add SPDX License identifier to header and specify file is part of LiteSATA. <Florent Kermarrec>
    * 2e4591c - getting started: update. <Florent Kermarrec>

 * litescope changed from 15179cb to 2020.08-2-g02b543e
    * 02b543e - litescope_cli: add capture subsampling support. <Florent Kermarrec>
    * 2739d5a - add SPDX License identifier to header and specify file is part of LiteScope. <Florent Kermarrec>
    * ec7bd6b - getting started: update. <Florent Kermarrec>
    *   7d22774 - Merge pull request timvideos#27 from cklarhorst/fix-storage-wrong-clock-domain <enjoy-digital>
    |\
    | * ad4e46c - Fix: 2 signals in the storage class belong to the wrong clock domain <Christian Klarhorst>
    |/
    *   2ad73a0 - Merge pull request timvideos#25 from cklarhorst/fix-trigger-flush-timer-wrong-clock-domain <enjoy-digital>
    |\
    | * 16e6555 - Fix: A WaitTimer belongs to the wrong clock domain (trigger flush) <Christian Klarhorst>
    |/
    * 0066866 - travis: install riscv toolchain for example. <Florent Kermarrec>
    * 6a322ed - test/test_examples: update. <Florent Kermarrec>
    * bc6c5e3 - examples: add mininal example on Arty with Etherbone and ibus/counter on analyzer. <Florent Kermarrec>
    * 0182377 - examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script. <Florent Kermarrec>
    * a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital>
    * 8b0274d - examples: add a more general script for testing <Jędrzej Boczar>

 * litex changed from 9fc488bd to 3897acb9
    * 3897acb9 - lattice/nx: update copyrights. <Florent Kermarrec>
    * 4364043b - integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone). <Florent Kermarrec>
    * 885c339d - soc/cores: add initial NX-LRAM support. <Piense>
    * cf13833e - cores/clock: add initial NX-OSCA support. <Piense>
    * e441bd60 - build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX). <Piense>
    *   8a44464a - Merge pull request timvideos#640 from antmicro/mor1kx_dt <enjoy-digital>
    |\
    | * 4dab1eb0 - litex_json2dts: Add support for mor1kx <Mateusz Holenko>
    * | 4f1c32ab - targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2. <Florent Kermarrec>
    * | d16051ff - boards/ulx3s: keep up to date with litex-boards. <Florent Kermarrec>
    * | d826c606 - soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values. <Florent Kermarrec>
    * | 9e37b16e - soc/interconnect/axi/AXILite2CSR: add register parameter for genericity. <Florent Kermarrec>
    |/
    *   42d8fc22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   ee0e2402 - Merge pull request timvideos#631 from gsomlo/gls-abc9-fixup <enjoy-digital>
    | |\
    | | * c4710b37 - build/lattice/trellis: make "-abc9" an optional argument <Gabriel Somlo>
    * | | 77ae2433 - test: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
    * | | b8371ef4 - tools: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
    * | | 93d906f9 - soc: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec>
    * | | e52ffd2d - gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. <Florent Kermarrec>
    * | | 70610b23 - build: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec>
    * | | 6ee882d1 - platforms/targets: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
    |/ /
    * | 9950e756 - build/io: fix InferedSDRIO (thanks @mtdudek). <Florent Kermarrec>
    * |   bae871a8 - Merge pull request timvideos#632 from gsomlo/gls-sdcard-refactor <enjoy-digital>
    |\ \
    | * | e0b2b815 - liblitesdcard/sdcard: read sdcard response only when needed <Gabriel Somlo>
    | * | a47b2de5 - sdcard: refactor command functions <Gabriel Somlo>
    | * | bfd6b3c3 - liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.) <Gabriel Somlo>
    | * | 37ebcd3b - factor out busy_wait_us() <Gabriel Somlo>
    | |/
    * |   3206dba9 - Merge pull request timvideos#636 from Xiretza/minerva-cli-filetype <enjoy-digital>
    |\ \
    | * | e3bb3a94 - Fix call to generation of minerva output file <Xiretza>
    | |/
    * |   8bc5dd7c - Merge pull request timvideos#635 from Xiretza/collections-abc-deprecation <enjoy-digital>
    |\ \
    | * | fcc7058b - Fix DeprecationWarning for collections.abc <Xiretza>
    | |/
    * |   79844362 - Merge pull request timvideos#634 from betrusted-io/spi_opi_timing_only <enjoy-digital>
    |\ \
    | |/
    |/|
    | * d783e86f - add a pipe register to relax an async_default timing path <bunnie>
    * | 35929c0f - soc/integration/csr_bridge: use registered version only when SDRAM is present. <Florent Kermarrec>
    * | e4f5dd98 - interconnect/wishbone/Wishbone2CSR: add registered version and use it as default. <Florent Kermarrec>
    * | b344196a - build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables). <Florent Kermarrec>
    * | f730f1d7 - cores/cpu/vexriscv_smp fix argument parsing <Dolu1990>
    * | 0e480dd6 - bios/main/sdram: fix speed reporting (Mbps/pin not MHz). <Florent Kermarrec>
    * |   bb7f3343 - Merge pull request timvideos#627 from gsomlo/gls-dma-addr-64 <enjoy-digital>
    |\ \
    | * | ba34c852 - cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address <Gabriel Somlo>
    |/ /
    * | 4cf28a01 - software/bios: display SDRAM databits and freq. <Florent Kermarrec>
    * | 6f69679d - cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses. <Florent Kermarrec>
    * | b3531cd2 - cores/cpu: add external cpu_type. <Florent Kermarrec>
    * | b9d3aab5 - targets: use platform.request_all on LedChaser. <Florent Kermarrec>
    * | 14c91664 - build/generic_platform: add request_all method. <Florent Kermarrec>
    * | 57335b99 - cores/cpu/zynq7000: simplify using new loose parameter of Platform.request. <Florent Kermarrec>
    * |   4867f2b3 - Merge pull request timvideos#624 from trabucayre/emio_zynq <enjoy-digital>
    |\ \
    | * | 87c26a30 - soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode <Gwenhael Goavec-Merou>
    * | | 48d63f23 - build/generic_plaform: add loose parameter to return None when not available/existing. <Florent Kermarrec>
    * | |   81df7b70 - Merge pull request timvideos#625 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \
    | * | | 2457859b - update BlackParrot transducer <sadullah>
    | * | | d2dabcef - Blackparrot human name update <sadullah>
    | |/ /
    * / / 188e6f57 - integration/soc/add_etherbone: pass phy to ethcore not self.ethphy. <Florent Kermarrec>
    |/ /
    * |   d5062d1f - Merge pull request timvideos#623 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \
    | * | 07a8e696 - cpu/vexriscv_smp Add --with-coherent-dma <Dolu1990>
    |/ /
    * | 9a4c5aa1 - integration/soc/add_sdram: update rules to connect main bus to dram. <Florent Kermarrec>
    * | a1644510 - cpu/vexriscv_smp: fix args_read. <Florent Kermarrec>
    * | 896b68cd - cpu/vexriscv_smp: cleanup, fix coherent_dma connection. <Florent Kermarrec>
    * |   342f359e - Merge pull request timvideos#622 from antmicro/fix_connectors <enjoy-digital>
    |\ \
    | * | de9ea19c - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan>
    * | | 3b293612 - soc/interconnect/axi: minor cleanups. <Florent Kermarrec>
    * | | 303d6cca - interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing. <Florent Kermarrec>
    * | | 00629c45 - interconnect/csr: add CSR registers ordering support. <Florent Kermarrec>
    * | | ee7a7f46 - soc/interconnect/csr: improve ident. <Florent Kermarrec>
    * | | b1008b01 - integration/soc: add expection on decoder when full address space is mapped. <Florent Kermarrec>
    * | | b831dc8c - wishbone: revert default adr_width to 30. <Florent Kermarrec>
    | |/
    |/|
    * | abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec>
    * | aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec>
    * |   b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital>
    |\ \
    | * | fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko>
    * | | 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec>
    * | | 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec>
    * | |   382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar>
    | * | c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar>
    | * | 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar>
    * | | e0f131a3 - cores/uart: add txempty/rxfull CSRs. <Florent Kermarrec>
    * | | 2a3e39b1 - tools/litex_server: enable read_merger with CommUDP. <Florent Kermarrec>
    * | | a5d0a340 - test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. <Florent Kermarrec>
    * | |   eb3374d0 - Merge pull request timvideos#617 from gsomlo/gls_rocket_dma <enjoy-digital>
    |\ \ \
    | * | | 561331ed - debug: make CI print offending values <Gabriel Somlo>
    | * | | df3428be - liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz <Gabriel Somlo>
    | * | | 2d9dc8f9 - cores/cpu/rocket: expose slave port for DMA <Gabriel Somlo>
    | * | | d8161e5a - integration/soc: make DMA slave region cover (at least) the lower 4GB <Gabriel Somlo>
    | * | | 70eae5cb - interconnect/wishbone: increase WB address width to 31 <Gabriel Somlo>
    | * | | b8c9da81 - soc/interconnect/axi: add Wishbone2AXI converter <Gabriel Somlo>
    |/ / /
    * | | 2ec4604c - cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. <Florent Kermarrec>
    * | |   5e53e5d7 - Merge pull request timvideos#615 from pepijndevos/openfpgaloader <enjoy-digital>
    |\ \ \
    | * | | 79ca4d96 - remove debugging <Pepijn de Vos>
    | * | | f6e20700 - add openFPGAloader programmer <Pepijn de Vos>
    * | | | eab0726c - cpu/vexriscv/core: use variant name as human_name. <Florent Kermarrec>
    * | | | e0a763e5 - cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. <Florent Kermarrec>
    * | | | 3ff1bcaf - cpu/zynq7000: set csr map to 0x00000000. <Florent Kermarrec>
    * | | |   c0253e3f - Merge pull request timvideos#611 from antmicro/jboc/axi-lite <enjoy-digital>
    |\ \ \ \
    | | |/ /
    | |/| |
    | * | | e78d950a - soc/interconnect/axi: add AXILite -> AXI converter <Jędrzej Boczar>
    * | | | cc844054 - tools/litex_server/read_merger: review/simplify a bit. <Florent Kermarrec>
    * | | |   4f382ccf - Merge pull request timvideos#605 from cklarhorst/feature-uart-read-merger <enjoy-digital>
    |\ \ \ \
    | * | | | 2034c563 - Merge sequential reads for the UART litex_server backend <Christian Klarhorst>
    * | | | | a942e358 - cpu/blackparrot: minor cleanups, add sim variant (since use different flist). <Florent Kermarrec>
    | |_|_|/
    |/| | |
    * | | |   86e910df - Merge pull request timvideos#610 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \ \ \
    | * | | | 023ab15e - soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth <Dolu1990>
    | * | | |   e5cd5d54 - Merge branch 'master' into vexriscv_smp <Dolu1990>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | 1938ce36 - integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. <Florent Kermarrec>
    * | | | | 6576416b - cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. <Florent Kermarrec>
    | * | | |   789a70e7 - Merge branch 'master' into vexriscv_smp <Dolu1990>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | 0696b409 - CHANGES: update. <Florent Kermarrec>
    * | | | | fe38e12b - cpu/vexriscv_smp: move litedram import, remove os.path import. <Florent Kermarrec>
    * | | | | 59b95fad - litex_setup: fix vexriscv-smp repository. <Florent Kermarrec>
    * | | | |   9d052f38 - Merge pull request timvideos#607 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \ \ \ \
    | | * | | | d284dfbe - soc/cores/cpu/vexriscv_smp config update <Dolu1990>
    | |/ / / /
    | * / / / aa57c7a2 - soc/cores/cpu/vexriscv_smp integration <Dolu1990>
    |/ / / /
    * | | | f87513ab - liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. <Florent Kermarrec>
    * | | | 9518ccf4 - integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). <Florent Kermarrec>
    | |_|/
    |/| |
    * | | 9e07623b - integration/soc: fix dma_bus typo. <Florent Kermarrec>
    |/ /
    * / 1fdffdfd - targets: keep in sync with litex-boards. <Florent Kermarrec>
    |/
    *   8a0684b1 - Merge pull request timvideos#604 from antmicro/jboc/axi-lite <enjoy-digital>
    |\
    | * 879e6ffe - soc/interconnect/axi: add basic AXI Lite up-converter <Jędrzej Boczar>
    | * 32160e61 - soc/interconnect/axi: separate AXI Lite converter channels <Jędrzej Boczar>
    * |   ed721198 - Merge pull request timvideos#603 from enjoy-digital/socdoc-extensions <Sean Cross>
    |\ \
    | * | 29b2baf9 - doc: socdoc: document new `sphinx_extra_config` parameter <Sean Cross>
    | * | dd366467 - litex: add `sphinx_extra_config` to `generate_docs()` <Sean Cross>
    * | | 3d16838d - Merge pull request timvideos#602 from enjoy-digital/socdoc-extensions <enjoy-digital>
    |\| |
    | * | 7fecfbf8 - doc: socdoc: document `sphinx_extensions` parameter <Sean Cross>
    |/ /
    * | 83370399 - CHANGES: update. <Florent Kermarrec>
    * | 041c7527 - core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. <Florent Kermarrec>
    |/
    * 8bdf6941 - liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). <Florent Kermarrec>
    * 8f92034d - CHANGES: update. <Florent Kermarrec>
    *   99e88dfc - Merge pull request timvideos#600 from antmicro/jboc/axi-lite <enjoy-digital>
    |\
    | * a9d8b813 - test/axi: move all AXI Lite tests to separate file <Jędrzej Boczar>
    | * 367eb122 - soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" <Jędrzej Boczar>
    | * 8ae501c3 - test/axi: add crossbar stress tests <Jędrzej Boczar>
    | * 706bc25d - soc/integration: add bus standard parser arguments <Jędrzej Boczar>
    | * 32d9e212 - soc/interconnect/axi: improve Timeout module and test it with shared interconnect <Jędrzej Boczar>
    | * 2cab7fbf - test/axi: add shared AXI Lite interconnect tests <Jędrzej Boczar>
    | * 3a08b21d - soc/interconnect/axi: implement AXI Lite decoder <Jędrzej Boczar>
    | * 214cfdca - soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to <Jędrzej Boczar>
    | * baf23c9c - test/test_axi: add AXI Lite interconnect arbiter tests <Jędrzej Boczar>
    | * a8a583d6 - socinterconnect/axi: interconnect shared sketch <Jędrzej Boczar>
    | * f47ccdae - soc/interconnect/axi: point-to-point interconnect and timeout module with tests <Jędrzej Boczar>
    | * b4c1120e - soc/integration: choose interconnect based on bus standard <Jędrzej Boczar>
    | * 69d8dd78 - soc/integration: add axi-lite standard to SoCBusHandler <Jędrzej Boczar>
    * | d38048ba - soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). <Florent Kermarrec>
    |/
    *   2361abb1 - Merge pull request timvideos#599 from antmicro/gen-mmcm-pr <enjoy-digital>
    |\
    | * 66c5f371 - litex-gen: add mmcm core <Piotr Binkowski>
    * 6b72f52c - boards: keep in sync with litex-boards. <Florent Kermarrec>
    * 1f27b740 - soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. <Florent Kermarrec>
    * 408d1a9f - cpu/vexriscv/system.h: update flush_cpu_dcache. <Florent Kermarrec>
    * 47ce15b4 - interconnect/wishbone: add minimal UpConverter. <Florent Kermarrec>

 * litex-boards changed from 2ce24df to 2020.08-9-g63b65e2
    * 63b65e2 - crosslink_nx_evn: update copyrights. <Florent Kermarrec>
    * 153326f - targets/icebreaker: update flash. <Florent Kermarrec>
    * 795e34a - add initial Crosslink-NX support. <Piense>
    * 84c19a6 - targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2. <Florent Kermarrec>
    * 70594a5 - ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. <Florent Kermarrec>
    * 1781be1 - general: add SPDX License identifier to header and specify files are part of LiteX-Boards. <Florent Kermarrec>
    * 83d8b8d - platforms/acorn_cle_215: integrated sdcard ios as extension. <Florent Kermarrec>
    *   d365836 - Merge pull request timvideos#100 from connorwk/master <enjoy-digital>
    |\
    | * f328909 - Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header. <connorwk>
    |/
    * 45bb329 - targets/colorlight_5a_75x: enable HalfRate SDRAM PHY. <Florent Kermarrec>
    * b6a1ad5 - targets/orangecrab: add simple CRG when built without DDR3. <Florent Kermarrec>
    * 869cead - targets: use platform.request_all on LedChaser. <Florent Kermarrec>
    *   8583c44 - Merge pull request timvideos#98 from antmicro/arty_pmod_configuration <enjoy-digital>
    |\
    | * d2cd6d4 - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan>
    |/
    * ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec>
    *   623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital>
    |\
    | * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos>
    |/
    * 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec>
    * 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec>
    * f058181 - README: fix typo. <Florent Kermarrec>
    * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec>
    * ecdc1ef - README: add missings . <Florent Kermarrec>
    * 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec>
    * 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec>
    * eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec>
    * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec>
    * bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec>
    * bb65692 - add LICENSE. <Florent Kermarrec>
    * e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec>
    * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec>
    * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec>
    * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec>
    * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec>
    * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec>
    * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec>
    *   89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital>
    |\
    | * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15>
    | * cf98393 - Add Misc <rob-ng15>
    * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec>
    * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec>
    |/
    * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec>
    * 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec>
    * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec>
    * 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec>

 * litex-renode changed from f179258 to 3d01f40
    * 3d01f40 - Merge pull request timvideos#29 from antmicro/i2c_generation <Mateusz Hołenko>
    * ed34c42 - generate-renode-scripts: Add I2C support <Mateusz Holenko>
    * a431211 - generate-zephyr-dts: Add I2C support <Mateusz Holenko>
    * 9f4f0fb - [FIX] Fix config generation <Mateusz Holenko>

 * nmigen changed from 8f5a253 to 1ad6e32
    * 1ad6e32 - Clifford -> Claire <Sebastien Bourdeauducq>
    * 40f7f12 - Add option to specify solver in nmigen.test.utils <Donald Sebastian Leung>

Full submodule status
--
 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06)
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 5c69da5d6db245dedab479509c0eaa8c1c80027c litedram (2020.08-3-g5c69da5)
 54acf9fd76c226d7760294ffde86418e52e0951b liteeth (2020.04-26-g54acf9f)
 efd200fa9e625144131a310fc09fd1fecf1682e6 liteiclink (2020.08-1-gefd200f)
 0718fd135fc30e0a3598eaf66ce2fcb54b62193c litepcie (2020.08-1-g0718fd1)
 ba006a78c12e25354dafb021510c043dbe070614 litesata (2020.08-1-gba006a7)
 02b543e5ba24c025212515f6e32f542629d823e8 litescope (2020.08-2-g02b543e)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
 3897acb9e4b91ad58abbcea8e3cff6e44223bd02 litex (2020.04-639-g3897acb9)
 63b65e278c279a9cf8c4da31db8f7e845edba394 litex-boards (2020.08-9-g63b65e2)
 3d01f408539b4641f9d2b42ebd8237436e49d16b litex-renode (remotes/origin/HEAD)
 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1)
 1ad6e3207f02e913407867dddddb8f50fad0ced4 nmigen (v0.1-71-g1ad6e32)
 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.08)
 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (2020.08)
 af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.08)
 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.08)
 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.08)
 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.08)
 da4c8c72eeb22894369b3936abb73f828f222b8e valentyusb (v0.3.3-195-gda4c8c7)
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