Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Reunite litex-buildenv with LiteX platforms #28

Open
13 tasks
cr1901 opened this issue May 17, 2018 · 2 comments
Open
13 tasks

Reunite litex-buildenv with LiteX platforms #28

cr1901 opened this issue May 17, 2018 · 2 comments

Comments

@cr1901
Copy link
Contributor

cr1901 commented May 17, 2018 •
edited by rohitk-singh
Loading

To reduce the amount of code duplication we should subclass from litex platforms' _io, connectors and methods instead of redefining them. This will prevent surprises and subtle incompatibilities between litex-buildenv and litex platforms if a user of litex-buildenv decides they want to use litex (or even migen) directly for their current project.

Contrived example: Maybe a user of litex wants complete customization for their shiny new project?

List of existing platforms:

  • arty.py
  • atlys.py
  • mimasv2.py
  • minispartan6.py
  • netv2.py
  • nexys_video.py
  • opsis.py
  • pipistrello.py

Platforms to add:

  • arty_s7.py
  • tinyfpga_b.py

The following are possibly okay leaving in litex-buildenv/not subclassing from LiteX?

  • sim.py
  • tofe_axiom.py
  • tofe_lowspeedio.py
@mithro
Copy link
Member

mithro commented May 17, 2018

There are more boards here too -> timvideos/HDMI2USB-litex-firmware#398

  • Digilent CMOD A7 (just platform file added)
  • Numato Lab Galatea Spartan 6 PCIe Development Board
  • Numato Lab Neso Artix 7 100T FPGA Module
  • Numato Lab Saturn Spartan 6 LX45 FPGA Module

mithro added a commit to mithro/litex-buildenv that referenced this issue Aug 23, 2018
@mithro
Updating submodules.
fe961e5 
 * edid-decode changed from dcc8b83 to e6d15fd
    * e6d15fd - This project has moved <Adam Jackson>

 * litedram changed from 45da365 to 06f841d
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-421-g0074bb88
    *   0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 e6d15fd33e2e81b483921cb23642dbd8f05e08d2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 06f841dc2a9db65469c18041a13d9f84568bb213 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 0074bb888c0e3ed20e4b1641d26fbb9bf2d05f81 litex (v0.1-421-g0074bb88)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
mithro added a commit to mithro/litex-buildenv that referenced this issue Aug 23, 2018
@mithro
Updating submodules.
2b2218b 
 * edid-decode changed from e6d15fd to b2da151
    * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
    * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
    * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
    * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
    * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
    * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
    * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
    * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
    * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
    * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
    * 7684918 - edid-decode: README: updates <Hans Verkuil>
    * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
    * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>

 * litedram changed from 45da365 to 06f841d
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-421-g0074bb88
    *   0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 06f841dc2a9db65469c18041a13d9f84568bb213 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 0074bb888c0e3ed20e4b1641d26fbb9bf2d05f81 litex (v0.1-421-g0074bb88)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
mithro added a commit to mithro/litex-buildenv that referenced this issue Aug 23, 2018
@mithro
Updating submodules.
8bfec2d 
 * edid-decode changed from e6d15fd to b2da151
    * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
    * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
    * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
    * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
    * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
    * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
    * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
    * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
    * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
    * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
    * 7684918 - edid-decode: README: updates <Hans Verkuil>
    * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
    * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>

 * litedram changed from 45da365 to 06f841d
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-421-g0074bb88
    *   0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 06f841dc2a9db65469c18041a13d9f84568bb213 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 0074bb888c0e3ed20e4b1641d26fbb9bf2d05f81 litex (v0.1-421-g0074bb88)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
ewenmcneill pushed a commit to ewenmcneill/litex-buildenv that referenced this issue Aug 27, 2018
@mithro @ewenmcneill
Updating submodules.
0b7e9a1 
 * edid-decode changed from e6d15fd to b2da151
    * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
    * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
    * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
    * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
    * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
    * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
    * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
    * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
    * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
    * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
    * 7684918 - edid-decode: README: updates <Hans Verkuil>
    * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
    * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>

 * litedram changed from 45da365 to 06f841d
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-421-g0074bb88
    *   0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 06f841dc2a9db65469c18041a13d9f84568bb213 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 0074bb888c0e3ed20e4b1641d26fbb9bf2d05f81 litex (v0.1-421-g0074bb88)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
ewenmcneill pushed a commit to ewenmcneill/litex-buildenv that referenced this issue Aug 27, 2018
@mithro @ewenmcneill
Updating submodules.
2ca8707 
 * edid-decode changed from e6d15fd to b2da151
    * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
    * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
    * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
    * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
    * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
    * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
    * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
    * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
    * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
    * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
    * 7684918 - edid-decode: README: updates <Hans Verkuil>
    * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
    * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>

 * litedram changed from 45da365 to 06f841d
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-421-g0074bb88
    *   0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 06f841dc2a9db65469c18041a13d9f84568bb213 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 0074bb888c0e3ed20e4b1641d26fbb9bf2d05f81 litex (v0.1-421-g0074bb88)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
mithro added a commit to ewenmcneill/litex-buildenv that referenced this issue Aug 27, 2018
@mithro
Updating submodules.
9916c81 
 * edid-decode changed from dcc8b83 to b2da151
    * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
    * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
    * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
    * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
    * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
    * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
    * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
    * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
    * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
    * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
    * 7684918 - edid-decode: README: updates <Hans Verkuil>
    * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
    * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>

 * litedram changed from 45da365 to 7a5ac75
    * 7a5ac75 - test/test_axi: improve test_axi2native <Florent Kermarrec>
    * d53832d - frontend/axi: split LiteDRAMAXI2Native (write path and read path) <Florent Kermarrec>
    * c846b8b - frontend/axi: add burst support (fixed/incr) <Florent Kermarrec>
    * 3fa77c8 - phy/s6ddrphy: use cwl only for DDR3 <Florent Kermarrec>
    * d9b5bb7 - frontend/bist: support axi with addressing in bytes <Florent Kermarrec>
    * 1370617 - frontend/axi: addressing in bytes not internal dwords <Florent Kermarrec>
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-423-g7a14b75c
    *   7a14b75c - Merge pull request timvideos#93 from phlipped/master <Tim Ansell>
    |\
    | * 8b51c445 - Fix URL for liteUSB <phlipped>
    |/
    *   0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 7a5ac75e2295dcf15f83df966244f30154a8f662 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 7a14b75cd676e9328063abc1fcdc6fcd4fc6c5ef litex (v0.1-423-g7a14b75c)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
@cr1901 cr1901 mentioned this issue Sep 23, 2018
Open
@cr1901 cr1901 mentioned this issue Oct 4, 2018
Merged
cr1901 added a commit to cr1901/litex-buildenv that referenced this issue Oct 4, 2018
@cr1901
Bump litex submodule for platform parity (see timvideos#28).
1ad548b
@mithro
Copy link
Member

mithro commented Jan 24, 2020

@piotr-binkowski

mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this issue Mar 5, 2020
@mateusz-holenko
Updating submodules.
91c94d2 
 * litedram changed from 8122209 to 8fee3c7
    * 8fee3c7 - test/reference: update kc705 ddr3_init.h. <Florent Kermarrec>

 * liteeth changed from f532a12 to 32d4af1
    * 32d4af1 - phy/__init__: import all phys. <Florent Kermarrec>
    * b2e1272 - phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints). <Florent Kermarrec>
    * 466223e - liteeth/gen: update copyrights <Florent Kermarrec>
    *   d6b5888 - Merge pull request timvideos#34 from Xiretza/generator-improvements <enjoy-digital>
    |\
    | * 7a44209 - Make memory/CSR regions customizable in config <Xiretza>
    | * ca9cbd1 - Move more options to config file <Xiretza>
    | * eea1086 - Use builder arguments in generator <Xiretza>
    | * b9fb1f0 - Remove leftover classes in generator <Xiretza>
    |/
    * 358bc23 - examples/.ymls: add separators <Florent Kermarrec>
    * ddcbc33 - test/test_gen: update <Florent Kermarrec>
    * fcadd60 - liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe) <Florent Kermarrec>
    *   b029088 - Merge branch 'ximinity-generator-lattice' <Florent Kermarrec>
    |\
    | * 0954fa3 - Merge branch 'generator-lattice' of git://github.com/ximinity/liteeth into ximinity-generator-lattice <Florent Kermarrec>
    |/|
    | * ae10eea - gen: add lattice support <Stefan Schrijvers>
    * |   fcf7b24 - Merge pull request timvideos#33 from Xiretza/standalone-features <enjoy-digital>
    |\ \
    | * | 5767dfc - Honour --output-dir argument in generator <Xiretza>
    | * | 153c160 - Prioritise overridden interrupts and memory regions <Xiretza>
    | * | ec9bc57 - Fix MII tx_en signal width in standalone generator <Xiretza>
    | * | 42a7b6c - Allow little-endian interface for standalone design <Xiretza>
    | * | a696ccd - Expose interrupt pin for standalone design <Xiretza>
    |/ /
    * | 208bc09 - liteeth/gen: update <Florent Kermarrec>
    * | ddd0431 - examples: use integrated sram instead of external one. (Also fix regression with new SoC that no longer support address decoders passed to add_wb_slave) <Florent Kermarrec>
    |/
    * 081bf46 - mac/sram: simplify code and improve SRAM read speed using async_read on Memory. <Florent Kermarrec>
    * bf4a11a - mac/sram: simplify counter (use NextValue in FSM) <Florent Kermarrec>
    * 721238b - mac/sram: cosmetic changes <Florent Kermarrec>

 * litepcie changed from c28ec23 to 10e520e
    * 10e520e - frotend/dma/synchronizer: expose synced signal. <Florent Kermarrec>

 * litevideo changed from 49bafa4 to 49d8126
    *   49d8126 - Merge pull request timvideos#30 from antmicro/netv2-edid <enjoy-digital>
    |\
    | * 4ab36eb - input/edid: add support for I2C configuration used on NeTV2 board <Piotr Binkowski>
    * |   2abfd6b - Merge pull request timvideos#29 from antmicro/iserdese2-clocking <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 19ecd23 - input/clocking: use BUFG for ISERDESE2 CLK net <Piotr Binkowski>
    |/
    *   72298a0 - Merge pull request timvideos#28 from antmicro/fifo-depth <enjoy-digital>
    |\
    | * 8c64782 - output/core: adjust fifo depth <Piotr Binkowski>
    |/
    *   5974ba8 - Merge pull request timvideos#27 from gregdavill/terminal-readback <enjoy-digital>
    |\
    | * 28d6f20 - terminal.core: Add read support via wishbone <Greg Davill>
    |/
    *   146d4a7 - Merge pull request timvideos#26 from FrankBuss/master <enjoy-digital>
    |\
    | * 7c24d18 - minor comments and example code cleanup <fb@frank-buss.de>
    |/
    * 7328d27 - terminal/core: remove obsolete vsync definition <Florent Kermarrec>
    * ab06562 - terminal: remove vga_clk parameter (a vga clock domain should exist in the SoC), add pads parameter and use it for hsync/vsync/r/g/b if Not None. <Florent Kermarrec>
    *   69e0757 - Merge pull request timvideos#25 from FrankBuss/master <enjoy-digital>
    |\
    | * 6d1831e - added missing files when installing it with "pip3 install ." <fb@frank-buss.de>
    |/
    * cb73fe9 - terminal/README: update <Florent Kermarrec>
    * 73ee69f - terminal/core: uniformize style with the others cores <Florent Kermarrec>
    * 31761ce - terminal/core: give more explict name to clk/clock_domain (vga_clk/cd_vga) <Florent Kermarrec>
    * 5e70963 - terminal/core: avoid exposing internal signals <Florent Kermarrec>
    * 9742f8a - Merge pull request timvideos#24 from FrankBuss/master <enjoy-digital>
    * 2ce9008 - VGA terminal emulation <fb@frank-buss.de>

 * litex changed from 02bfda5e to 9249fc90
    *   9249fc90 - Merge pull request timvideos#410 from antmicro/netv2-edid <enjoy-digital>
    |\
    | * 72f63243 - platform/netv2: add proper I2C pins for HDMI IN0 <Piotr Binkowski>
    * | ad11ff39 - targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. <Florent Kermarrec>
    * | 37701950 - bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes. <Florent Kermarrec>
    * | 4c83c975 - doc: align to improve readability. <Florent Kermarrec>
    * | 4f935714 - soc/doc: remove soc.get_csr_regions support. <Florent Kermarrec>
    * | 6893222c - bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help. <Florent Kermarrec>
    * | d2accbb1 - README: update quick start guide and add instructions for windows. <Florent Kermarrec>
    * | fc9b3975 - README: update - improve presentation - add link to #litex freenode channel. - add example of complex SoC. - make it directly usable on Wiki. - only keep one quick start guide. - add community paragraph and link to Litex-Hub. <Florent Kermarrec>
    * | 68f56542 - doc: remove partial doc imported from litex-buildenv-wiki: we'll create a LiteX wiki and doc. <Florent Kermarrec>
    * | 0b923aa4 - build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters. <Florent Kermarrec>
    * | 1d7c6943 - software/common: add LTO enable flag and cleanup. <Florent Kermarrec>
    * | b29f443f - litex_sim: fix with_uart parameter. <Florent Kermarrec>
    |/
    * 98e41e2e - targets/nexys4ddr: add default kwargs parameters. <Florent Kermarrec>
    *   598ad692 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   ddb264f3 - Merge pull request timvideos#405 from sajattack/sifive-triple <enjoy-digital>
    | |\
    | | * 68c013d1 - add riscv-sifive-elf triple <Paul Sajna>
    * | | a67e19c6 - integration/soc_core: change disable parameters to no-xxyy. <Florent Kermarrec>
    * | | 156a85b1 - integration/soc: add auto_int type and use it on all int parameters. <Florent Kermarrec>
    * | | 7e96c911 - targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM. <Florent Kermarrec>
    * | | cb0371b3 - integration/soc: add ethphy CSR in target. <Florent Kermarrec>
    |/ /
    * | f27225c2 - targets/nexys4ddr: use soc.add_ethernet method. <Florent Kermarrec>
    * | 9735bd5b - integration/soc: add add_ethernet method. <Florent Kermarrec>
    * | 1c74143a - integration/soc: mode litedram imports to add_sdram, remove some separators. <Florent Kermarrec>
    |/
    * 54fb3a61 - test/test_targets: use uart-name=stub. <Florent Kermarrec>
    * 59e99bfb - soc/uart: add configurable UART FIFO depth. <Florent Kermarrec>
    * 9199306a - cores/uart: cleanup <Florent Kermarrec>
    * ea856333 - soc/cores/uart/UARTCrossover: reduce fifo_depth to 1. <Florent Kermarrec>
    * 12a75286 - interconnect/stream/SyncFIFO: allow depth down to 0. <Florent Kermarrec>
    * 9e31bf35 - interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface. <Florent Kermarrec>
    * 1e0e96f9 - interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods. <Florent Kermarrec>
    * 6be7e9c3 - interconnect/axi: set default data_width/address_width to 32-bit. <Florent Kermarrec>
    * 8e1d5286 - targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). <Florent Kermarrec>
    * a7c5dd5d - cores/gpio: use separate TSTriple for each bit. <Florent Kermarrec>
    * 400492e2 - lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends. <Florent Kermarrec>
    * c4fd6a7f - targets/kc705: use DDRPHY_CMD_DELAY to center write leveling. <Florent Kermarrec>
    * 78a32235 - software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling. <Florent Kermarrec>
    * eab5161d - boards: keep in sync with LiteX-boards <Florent Kermarrec>
    * 935e4eff - interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests) <Florent Kermarrec>
    * d324c54e - integration/soc: -x on soc.py <Florent Kermarrec>
    * ee27a9e5 - soc/cores/bitbang: fix missing self.comb on miso. <Florent Kermarrec>
    *   a2d69869 - Merge pull request timvideos#402 from antmicro/litex-gen-fix-uart-pins <enjoy-digital>
    |\
    | * 75b000a3 - tools: litex_gen: fix missing UART pins <Jan Kowalewski>
    * | e2aebb42 - software: disable LTO with LM32 (not supported by old GCC versions easily available). <Florent Kermarrec>
    * |   9e70fcf8 - Merge pull request timvideos#401 from antmicro/enable-lto <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 718a65c3 - software: enable link time optimization (LTO) <Tim 'mithro' Ansell>
    |/
    *   9521f2ff - Merge pull request timvideos#400 from Xiretza/ecp5-pll-freqfix <enjoy-digital>
    |\
    | * 7a87d4e2 - Fix ECP5PLL VCO frequency range <Xiretza>
    |/
    * 0c7e0bf0 - integration/soc: improve presentation of SoCLocHandler's locations. <Florent Kermarrec>
    * 0042a028 - interconnect/axi: remove bus_name on connect_to_pads <Florent Kermarrec>
    * 5aba1fe8 - tools/litex_gen: add bus parameter and AXI (Lite) support. <Florent Kermarrec>
    * a3584147 - litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads. <Florent Kermarrec>
    * d86db6f1 - litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads. <Florent Kermarrec>
    * 18c57a64 - tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify. <Florent Kermarrec>
    *   0083e097 - Merge pull request timvideos#396 from antmicro/external-wb <enjoy-digital>
    |\
    | * 9e2aede8 - tools: add script for extracting wishbone cores <Piotr Binkowski>
    | * 79a14001 - axi: add to_pads method <Karol Gugala>
    | * e0bcb57d - wishbone: add extracting module signals to the top <Jan Kowalewski>
    * |   017c91a4 - Merge pull request timvideos#397 from gsomlo/gls-csr-volatile <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 173117ad - Add 'volatile' qualifier to new CSR accessors <Gabriel Somlo>
    |/
    * 485934ed - doc/socdoc: fix example <Florent Kermarrec>
    * 53ee9a5e - cpu/blackparrot: first cleanup pass <Florent Kermarrec>
    * f3829cf0 - integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs. <Florent Kermarrec>
    * 3a6f97ff - build/sim: add Verilator FST tracing support. <Florent Kermarrec>
    *   8a715f3b - Merge pull request timvideos#390 from gsomlo/gls-add-sdcard <enjoy-digital>
    |\
    | * 516cf405 - targets/nexys4ddr: add optional sdcard support <Gabriel Somlo>
    | * d4d2b7f7 - bios: add litesdcard test routines to boot menu <Gabriel Somlo>
    | * 7a2e33b8 - targets/nexys4ddr: add ethernet via method instead of inheritance <Gabriel Somlo>
    |/
    * 774a55a2 - soc_core: fix missing init on main_ram <Florent Kermarrec>
    *   5d580ca4 - Merge pull request timvideos#389 from antmicro/linux_flash_offsets <enjoy-digital>
    |\
    | * 659c244a - bios/boot: allow to customize flash offsets of Linux images <Mateusz Holenko>
    * | 00895518 - cores/cpu: use standard+debug variant when only debug is specified. <Florent Kermarrec>
    |/
    * ae45be47 - soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL <Florent Kermarrec>
    * 9baa3ad5 - soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment) <Florent Kermarrec>
    * 854e7cc9 - integration/soc: improve Region logger <Florent Kermarrec>
    * 9cb8f68e - bios/boot: update and fix flashboot, improve verbosity <Florent Kermarrec>
    * 6ed0f445 - soc: increase supporteds address_width/paging <Florent Kermarrec>
    * 5b3808cb - soc_core: expose CSR paging <Florent Kermarrec>
    * 0497f3ca - soc/csr_bus: improve CSR paging genericity <Florent Kermarrec>
    * 351896bf - tools/litex_sim: use new sdram verbosity parameter <Florent Kermarrec>
    * 67e8a042 - integration/soc: add configurable CSR Paging <Florent Kermarrec>
    * 65764701 - soc_core: add back identifier <Florent Kermarrec>
    *   8f6114d0 - Merge pull request timvideos#387 from BracketMaster/master <enjoy-digital>
    |\
    | * 3da204ed - update to work with mac <Yehowshua Immanuel>
    * | 3574b909 - tools/litex_sim: specify default local/remote-ip addresses. <Florent Kermarrec>
    * | aebaea77 - tools/litex_sim: add ethernet local/remote-ip arguments. <Florent Kermarrec>
    |/
    * 18a9d4ff - interconnect/stream: cleanup imports/idents <Florent Kermarrec>
    *   57fb3720 - Merge pull request timvideos#386 from antmicro/sdram-timing-checker <enjoy-digital>
    |\
    | * eff85a99 - tools/litex_sim: add cli options to control SDRAM timing checker <Piotr Binkowski>
    |/
    * e4712ff7 - soc_core: fix cpu_variant renaming regression <Florent Kermarrec>
    * a2f1683b - doc: rename lxsocdoc -> socdoc and update readme <Sean Cross>
    * baa29f1b - doc: fix regression with new irq manager <Sean Cross>
    * 1620f9c5 - soc/CSR: show alignment in report and add info when updating. <Florent Kermarrec>
    * 5b34f4cd - soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket <Florent Kermarrec>
    * 2f69f607 - integration/soc: fix refactoring issues <Florent Kermarrec>
    * 1d6ce66b - soc/integration/builder: update copyright, align arguments <Florent Kermarrec>
    *   98ae91ad - Merge pull request timvideos#383 from Xiretza/builder-directories <enjoy-digital>
    |\
    | * b5654579 - Unify output directory handling in builder <Xiretza>
    |/
    *   4a15c3e2 - Merge pull request timvideos#382 from enjoy-digital/new_soc <enjoy-digital>
    |\
    | * e9c665a5 - soc_core/soc_sdram: add disclaimer <Florent Kermarrec>
    | * 5558865c - soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region <Florent Kermarrec>
    | * 1b5caf56 - soc: fix busword typo <Florent Kermarrec>
    | * 8b5cc345 - targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) <Florent Kermarrec>
    | *   240a55ba - Merge branch 'master' into new_soc <enjoy-digital>
    | |\
    | |/
    |/|
    * | d5ad1d56 - soc/integration: move mem_decoder to soc_core <Florent Kermarrec>
    * | 0a737cb6 - soc/integration/common: simplify get_version <Florent Kermarrec>
    * | 4d761e1a - cores/cpu: remove separators on io_regions (requires python 3.6) <Florent Kermarrec>
    * |   7c57a33b - Merge pull request timvideos#380 from Xiretza/cpunone-all-io <enjoy-digital>
    |\ \
    | * | e301df7f - Allow all memory regions to be used as IO with CPUNone <Xiretza>
    |/ /
    * | 16d1972b - integration/common: fix mem_decoder (shadow base has been deprecated) <Florent Kermarrec>
    * | 7ee9ce38 - .gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules) <Florent Kermarrec>
    * |   1dced818 - Merge pull request timvideos#278 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \
    | * | d15c911c - BlackParrot initial commit w/ Litex BIOS simulation including LiteDRAM w/ Litex BIOS working on FPGA excluding LiteDRAM <sadullah>
    * | | 1d70ef69 - soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now) <Florent Kermarrec>
    * | | 62f3537d - soc/cores: rename spiopi to spi_opi <Florent Kermarrec>
    * | | f58e8188 - soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. <Florent Kermarrec>
    * | |   c2c80b5d - Merge pull request timvideos#378 from betrusted-io/merge_ip <enjoy-digital>
    |\ \ \
    | * | | 98e46c27 - reduce indents <bunnie>
    | * | | d2b394a9 - update doc comments on events for i2s <bunnie>
    | * | | 416afd31 - add doc comment for event <bunnie>
    | * | | 33d9e45a - fix formatting on spiopi <bunnie>
    | * | | cc6ed667 - Request to merge I2S and SPIOPI cores <bunnie>
    | | | * 399b65fa - soc/add_uart: fix bridge <Florent Kermarrec>
    | | | * 160c55d1 - soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted) <Florent Kermarrec>
    | | | * b2c66b1e - soc: avoid double definition of main_ram <Florent Kermarrec>
    | | | * 5f994608 - soc: improve log colors on error reporting <Florent Kermarrec>
    | | | * b22d2ca0 - soc: add linker regions management <Florent Kermarrec>
    | | | * abc31a92 - soc: improve log presentation/colors <Florent Kermarrec>
    | | | * 91e2797b - soc: fix cpu_reset_address <Florent Kermarrec>
    | | | * 0d7430fc - tools/litex_sim_new: remove <Florent Kermarrec>
    | | | * 21d38701 - soc: fix build_time format <Florent Kermarrec>
    | | | * b43d830f - soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices) <Florent Kermarrec>
    | | | * ea8e745a - soc_core/common: move old mem_decoder to soc_core, simplify get_version <Florent Kermarrec>
    | | | * 5e11e839 - tools/litex_sim_new: switch to dynamically allocated ethmac origin <Florent Kermarrec>
    | | | * dd0c71d7 - soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin <Florent Kermarrec>
    | | | * e8e4537e - soc/add_sdram: avoid L2 cache when l2_cache_size == 0. <Florent Kermarrec>
    | | | * dcbdb732 - soc: remove unneeded \n <Florent Kermarrec>
    | | | * 0f1811fb - tools/litex_sim_new: use new bus/csr/irq methods <Florent Kermarrec>
    | | | * d320be8e - soc: use io_regions for alloc_region <Florent Kermarrec>
    | | | * 9ac09ddd - tools: add litex_sim_new based on SoCCore and using add_sdram method <Florent Kermarrec>
    | | | * cbcd953d - soc_core: use add_rom <Florent Kermarrec>
    | | | * 487ac3da - soc/add_cpu: simplify CPUNone integration <Florent Kermarrec>
    | | | * f7d4648c - soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus <Florent Kermarrec>
    | | | * 379d47a8 - soc/add_sdram: add sdram csr <Florent Kermarrec>
    | | | * 3921b634 - soc/add_sdram: fix rocket, shorten comments <Florent Kermarrec>
    | | | * 14b627b4 - soc/add_sdram: improve API <Florent Kermarrec>
    | | | * 1faefdc0 - soc: add LiteXSoC class and mode add_identifier/uart/sdram to it <Florent Kermarrec>
    | | | * 11dbe190 - soc_core/sdram: cleanup, add disclaimer <Florent Kermarrec>
    | | | * 5eb88cd9 - soc: add add_sdram <Florent Kermarrec>
    | | | * 39011593 - soc: add csr_regions, update copyright <Florent Kermarrec>
    | | | * d2b06951 - soc: add cpu rom/sram check <Florent Kermarrec>
    | | | * de100fdd - soc: add SOCIORegion and manage it <Florent Kermarrec>
    | | | * 6b8c425f - soc: reorder main components/peripherals <Florent Kermarrec>
    | | | * 84b5df78 - soc: add add_cpu method <Florent Kermarrec>
    | | | * b676a559 - soc: fix unit-tests <Florent Kermarrec>
    | | | * 0a588390 - soc: integrate constants/build <Florent Kermarrec>
    | | | * 014d5a56 - soc: show sorted regions (by origin) / locs <Florent Kermarrec>
    | | | * c69b6b7c - soc: simplify color theme <Florent Kermarrec>
    | | | * 3cb90297 - soc: add add_uart method <Florent Kermarrec>
    | | | * e5cacb8b - soc_core: cleanup imports <Florent Kermarrec>
    | | | * 33d498b8 - soc_core: get_csr_address no longer used <Florent Kermarrec>
    | | | * 1feff1d7 - soc: integrate CSR master/interconnect/collection and IRQ collection <Florent Kermarrec>
    | | | * 3ba7c29e - soc: add add_constant/add_config methods <Florent Kermarrec>
    | | | * 29bbe4c0 - soc: add add_csr_bridge method <Florent Kermarrec>
    | | | * b84c291c - soc: add add_controller/add_identifier/add_timer methods <Florent Kermarrec>
    | | | * 9445c33e - soc: add add_ram/add_rom methods <Florent Kermarrec>
    | | | * e5a8ac1d - soc: add automatic bus data width convertion to add_master/add_slave <Florent Kermarrec>
    | | | * 8f67f115 - soc/soc_core: cleanup, remove some unused attributes <Florent Kermarrec>
    | | | * 2c6e5066 - soc: move SoCController from soc_core to soc <Florent Kermarrec>
    | | | * 848fa20d - soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler <Florent Kermarrec>
    | | | * 39458c92 - soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined <Florent Kermarrec>
    | | | * 1eff0799 - soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined <Florent Kermarrec>
    | | | * 8bc42067 - soc/integration: initial adaptation to new SoC class <Florent Kermarrec>
    | | | * 6baa07a6 - soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC <Florent Kermarrec>
    | |_|/
    |/| |
    * | | 9b11e919 - cpu/vexriscv: update submodule <Florent Kermarrec>
    |/ /
    * | ae085782 - doc: add lxsocdoc.md (README from lxsocdoc repository) <Sean Cross>
    * |   5ff02e23 - Merge pull request timvideos#375 from xobs/add-lxsocdoc <enjoy-digital>
    |\ \
    | * | 58598d4f - integration: svd: move svd generation to `export` <Sean Cross>
    | * | 73ed7e56 - soc: doc: use sphinx toctree as it was intended <Sean Cross>
    | * | 7c3bc0b0 - litex-doc: initial merge of lxsocdoc <Sean Cross>
    * | | 1944d8d9 - bios/main: add LiteX tagline <Florent Kermarrec>
    * | |   40cddca9 - Merge pull request timvideos#376 from antmicro/build-sim-do-not-override-C-LD-FLAGS <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 90fe5850 - build/sim: allow to use environment's {C,LD}FLAGS <Mariusz Glebocki>
    |/ /
    * |   bd6fd3da - Merge pull request timvideos#373 from antmicro/l2-reverse <enjoy-digital>
    |\ \
    | * | f3b068e2 - tools/litex_sim: use l2_reverse flag <Piotr Binkowski>
    |/ /
    * | 3350d33f - wishbone/Cache: add reverse parameter <Florent Kermarrec>
    * | eff9caee - soc_sdram: add l2_reverse parameter <Florent Kermarrec>
    * |   6e5b47f4 - Merge pull request timvideos#370 from Disasm/fixes <enjoy-digital>
    |\ \
    | * | de88ed28 - Fix argument descriptions <Vadim Kaushan>
    | * | eb49ec21 - Pass --csr-json to the Builder <Vadim Kaushan>
    |/ /
    * | b69f2993 - soc_core: add UART bridge support (simplify having to do it externally) <Florent Kermarrec>
    * | 7a6c04db - build/altera/quartus: fix fmt_r typo <Florent Kermarrec>
    * | c6b9676d - cpu/minerva: update (use new nMigen API) <Florent Kermarrec>
    * | 9d289472 - inteconnect/stream: use PipeValid implementation for Buffer <Florent Kermarrec>
    * | 1c88c0f8 - inteconnect/stream: cleanup <Florent Kermarrec>
    * |   cafd9c35 - Merge pull request timvideos#366 from gsomlo/gls-csr-followup <enjoy-digital>
    |\ \
    | * | ff2775c2 - software, integration/export: (re-)expose CSR subregister accessors <Gabriel Somlo>
    * | | f3f9808d - interconnect/stream: add PipeValid and PipeWait to cut timing paths. <Florent Kermarrec>
    * | | b22ad1ac - build/xilinx/vivado: improve readability of generated tcl/xdc files <Florent Kermarrec>
    |/ /
    * | 7bc34a9b - integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM). <Florent Kermarrec>
    * |   b4b56db4 - Merge pull request timvideos#363 from antmicro/litex-sim-ddr4 <enjoy-digital>
    |\ \
    | * | c02dd5e8 - tools/litex_sim: add ddr4 PhySettings <Piotr Binkowski>
    |/ /
    * | 0820adbd - tools/litex_sim: add --sdram-init parameter <Florent Kermarrec>
    * | 01ae10b8 - software/bios: revert M-Labs MiSoC copyright. <Florent Kermarrec>
    * | ea5ef8c1 - README: update copyright year and make sure LICENSE/README both mention MiSoC <Florent Kermarrec>
    * | 95cfa6a8 - platforms/netv2: add pcie pins <Florent Kermarrec>
    * |   f9bc98ed - Merge pull request timvideos#359 from gregdavill/bios_ddr3_ecp5 <enjoy-digital>
    |\ \
    | * | 1f439062 - soc/software/bios/sdram: ECP5 move strobe dly_sel <Greg Davill>
    | * | f84f57d6 - soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling <Greg Davill>
    |/ /
    * | 52765488 - tools/litex_sim: update copyrights and cosmetic changes <Florent Kermarrec>
    * |   b280bb2f - Merge pull request timvideos#358 from antmicro/litex_sim_ddr <enjoy-digital>
    |\ \
    | * | 9aa97c2e - tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3) <Piotr Binkowski>
    * | | 19ef19ce - cores/clock/create_clkout: rename clk_ce to ce, improve error reporting <Florent Kermarrec>
    * | |   7e088360 - Merge pull request timvideos#357 from betrusted-io/add_clk_ce <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 1f7549b4 - add BUFIO to clockgen buffer options <bunnie>
    | * | b3f9aa11 - add option for BUFGCE to the clock generator buffer types <bunnie>
    * | | cbc081c4 - tools/litex_sim: review/cleanup sdram-module/sdram-data-width features. <Florent Kermarrec>
    * | |   b35ea459 - Merge pull request timvideos#354 from antmicro/litex_sim_ddr <enjoy-digital>
    |\ \ \
    | * | | 674cfcde - tools/litex_sim: specify dram chip and data width via commandline <Piotr Binkowski>
    * | | |   b23f13d9 - Merge pull request timvideos#351 from antmicro/fix_sram_size_argument <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | * | | 7a05353a - soc_core: rename integrated_sram_size argument <Mateusz Holenko>
    | * | | c4bb4169 - soc_core: fix integrated_sram_size argument type <Mateusz Holenko>
    * | | | 5845df76 - build/xilinx/vivado: add pre_placement/pre_routing commands <Florent Kermarrec>
    * | | | 13880882 - cores/icap: add add_timing_constraints method <Florent Kermarrec>
    * | | | 2074a86e - cores/dna: cleanup and add add_timing_constraints method <Florent Kermarrec>
    |/ / /
    * | | d39dc8cf - tools/litex_sim: cleanup/simplify <Florent Kermarrec>
    * | | a0d95766 - build/sim: add -Wl,--no-as-needed to LDFLAGS for Ubuntu 16.04 support (thanks kamejoko80) <Florent Kermarrec>
    * | | 80c3dc41 - targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) <Florent Kermarrec>
    * | | 53bc18cc - soc_core: add new alloc_mem/add_mem_region to allow automatic allocation of memory regions <Florent Kermarrec>
    |/ /
    * | eae0e004 - cores/clock/xadc: ease DRP timings <bunnie>
    * | 7b92a17c - test/test_targets: limit max_sdram_size to 1GB <Florent Kermarrec>
    * | 008a0894 - targets/nexys4ddr: fix typo <Florent Kermarrec>
    * | 36e5274a - SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map) <Florent Kermarrec>
    * | 46c1c5c1 - targets/kcu105: remove main_ram_size_limit <Florent Kermarrec>
    * | 5913c91c - SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user <Florent Kermarrec>
    * | 1c465f89 - build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file <Florent Kermarrec>
    * | b4ba2a47 - soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover <Florent Kermarrec>
    |/
    * 5aa516cb - soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read. <Florent Kermarrec>
    * 862e784e - cpu/vexriscv: use 32-bit signal for externalResetVector <Florent Kermarrec>
    * f2a1673f - targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection <Florent Kermarrec>
    * 990870d0 - targets/genesys2: add EtherboneSoC <Florent Kermarrec>
    * 820e79bf - platforms/de0nano: specify gpio for serial <Florent Kermarrec>
    * ba366d42 - targets: cleanup EthernetSoC <Florent Kermarrec>
    * a2685370 - soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. <Florent Kermarrec>
    * a168ecba - targets/arty: add EtherboneSoC <Florent Kermarrec>
    * 7a4ecfa5 - targets/kcu105: update <Florent Kermarrec>
    * 68e225fb - test/test_targets: update <Florent Kermarrec>
    * 42efa998 - SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args. <Florent Kermarrec>
    * 4050e608 - SoCCore: use hex for integrated_rom/sram_size <Florent Kermarrec>
    *   f818755c - Merge pull request timvideos#339 from gsomlo/gls-csr-cleanup <enjoy-digital>
    |\
    | * b073ebad - bios/sdram: switch to updated CSR accessors, and misc. cleanup <Gabriel Somlo>
    | * 2c393041 - software, integration/export: rename and reimplement CSR accessors <Gabriel Somlo>
    * | f1606dbc - tools/litex_sim: use default integrated_rom_size <Florent Kermarrec>
    * | 4648db0c - cores/uart/UARTInterface: remove connect method <Florent Kermarrec>
    * | 6c9f418d - soc_core: fix uart stub <Florent Kermarrec>
    |/
    * 63cd23c9 - cpu/vexriscv: revert mem_map_linux/main_ram <Florent Kermarrec>
    * 83a7225c - SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets <Florent Kermarrec>
    * 6e3f25a7 - cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000 <Florent Kermarrec>
    * fe14b9cf - targets/genesys2: update self.register_sdram <Florent Kermarrec>
    * 39ce39a2 - soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency. <Florent Kermarrec>
    * 23175190 - cores/uart: add UARTCrossover <Florent Kermarrec>
    * 2f03d323 - cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover. <Florent Kermarrec>
    * d92bd8ff - gen/fhdl/verilog: fix signed init values <Florent Kermarrec>
    *   ff066a5e - Merge pull request timvideos#338 from DurandA/master <enjoy-digital>
    |\
    | * d24a4b54 - Add optional 'ignore-loops' flag to nextpnr <Arnaud Durand>
    * | 26fe45fc - cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator" <Florent Kermarrec>
    * |   d40bf9d8 - Merge pull request timvideos#340 from xobs/bridged-uart <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 5079a3c3 - uart: add BridgedUart <Sean Cross>
    |/
    * f70dd482 - bios/sdram: add memspeed <Florent Kermarrec>
    * fa22d6aa - wishbone/Cache: avoid REFILL_WRTAG state to improve speed. <Florent Kermarrec>
    * f408527d - soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. <Florent Kermarrec>
    * 8889821c - targets: sync with litex-boards <Florent Kermarrec>
    * aba8fc5c - build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar. <Florent Kermarrec>
    *   e318287e - Merge pull request timvideos#337 from gregdavill/spi-flash <enjoy-digital>
    |\
    | * 49781467 - soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging <Greg Davill>
    * | 2cf95e9f - platforms/minispartan6: rename sd to sdcard and regroup data lines <Florent Kermarrec>
    * | e99740e8 - platforms/nexys4ddr: add sdcard pins <Florent Kermarrec>
    * | 83ad674f - build/lattice/trellis: use a single fonction to parse device <Florent Kermarrec>
    * |   018c7ca8 - Merge pull request timvideos#336 from kbeckmann/trellis-speed <enjoy-digital>
    |\ \
    | * | 426ab676 - trellis: Pass speed grade argument to nextpnr <Konrad Beckmann>
    |/ /
    * |   fd4cbd80 - Merge pull request timvideos#331 from betrusted-io/xadc_mods <enjoy-digital>
    |\ \
    | * | 378722a7 - soc/cores/xadc: define analog_layout and simplify analog_pads connections <Florent Kermarrec>
    | * | 87d456ca - bring back analog_pads specifier, remove reset conditions on VP <bunnie>
    | * | 4dc0a614 - soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed. <Florent Kermarrec>
    | * | 5eec7432 - fix a couple bugs in the DRP readout path <bunnie>
    | * | 56ccaeeb - add support for DRP on XADC <bunnie>
    * | | 642d0737 - cpu/minerva: fix variant syntax warning <Florent Kermarrec>
    * | |   8ba204c7 - Merge pull request timvideos#332 from gsomlo/gls-csr-mem-sel <enjoy-digital>
    |\ \ \
    | * | | d087e2e0 - interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs) <Gabriel Somlo>
    |/ / /
    * | | 690de79d - cpu/microwatt: reorder sources, add comments <Florent Kermarrec>
    * | | e36df2a6 - build/lattice/icestorm: increase similarities with trellis. <Florent Kermarrec>
    * | | 197edad3 - soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description <Florent Kermarrec>
    * | | b65a36e7 - soc/integration/soc_core/SoCController: rephrase CSR descriptions a bit <Florent Kermarrec>
    * | |   1f27b21f - Merge pull request timvideos#330 from xobs/document-ctrl-timer0 <enjoy-digital>
    |\ \ \
    | * | | c5aa929d - cores: timer: clean up wording for timer documentation <Sean Cross>
    | * | | 2d75aee7 - soc_core: ctrl: document registers <Sean Cross>
    | * | | a251d712 - cores: timer: fix documentation formatting <Sean Cross>
    |/ / /
    * | | db7a48c0 - soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL <Florent Kermarrec>
    * | | caacc411 - Merge pull request timvideos#328 from betrusted-io/precise_clocks <enjoy-digital>
    |\| |
    | * | 219bb7f2 - add the possibility for a "precise" clock solution <bunnie>
    |/ /
    * | 9336fe11 - build/microsemi/libero_soc: update add_period_constraint behavior when clock is already constrainted. <Florent Kermarrec>
    * | 3022f02b - build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted. <Florent Kermarrec>
    * | fe4eaf58 - build/lattice/icestorm/add_period_constraint: improve <Florent Kermarrec>
    * | 6b91e882 - soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so <Florent Kermarrec>
    * |   2157d0f3 - Merge pull request timvideos#327 from zakgi/master <enjoy-digital>
    |\ \
    | * | 39ae230b - moving RAM offsets outside of CSR_ETHMAC define <Giammarco Zacheo>
    * | | f0b5c672 - Allow specifying the same clock constraint multiple times. <Tim 'mithro' Ansell>
    * | | 8b955e6f - Allow LiteX builder to be used without LiteDRAM. <Tim 'mithro' Ansell>
    * | | a738739a - Improve the invalid CPU type error message. <Tim 'mithro' Ansell>
    * | | 85ade2b3 - build/xilinx/programmer: fix vivado_cmd when settings are sourced manually. <Florent Kermarrec>
    |/ /
    * |   ffa7ca8f - Merge pull request timvideos#321 from gsomlo/gls-rocket-aximem-wide <enjoy-digital>
    |\ \
    | * | cd8feca5 - cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi <Gabriel Somlo>
    * | |   e754c055 - Merge pull request timvideos#319 from DurandA/feature-integer-attributes <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 94e239ff - Add integer attributes <Arnaud Durand>
    | * | f8c58216 - Revert "gen/fhdl/verilog: allow single element verilog inline attribute" <Arnaud Durand>
    * | |   40c35550 - Merge pull request timvideos#320 from gsomlo/gls-touch-up <enjoy-digital>
    |\ \ \
    | * | | 585b50b2 - soc_core: csr_alignment assertions <Gabriel Somlo>
    | * | | b6818c20 - cpu/rocket: access PLIC registers via pointer dereference <Gabriel Somlo>
    |/ / /
    * / / 0e46913d - cpu/microwatt: add initial software support <Florent Kermarrec>
    |/ /
    * | f883f0c7 - cpu/microwatt: add submodule <Florent Kermarrec>
    * | 5da0bcbd - cpu/microwatt: set csr to 0xc0000000 (IO region) <Florent Kermarrec>
    * | 39a8ebe7 - cpu/microwatt: fix add_source/add_sources <Florent Kermarrec>
    * | d74a7463 - soc/cores/pwm: remove debug print(n) <Florent Kermarrec>
    * | bd15f07c - platforms/netv2: add xc7a100t support <Florent Kermarrec>
    * | 76e57414 - platforms/minispartan6: add assert on available devices <Florent Kermarrec>
    * | bfe0bf64 - cpu/microwatt: simplify add_sources <Florent Kermarrec>
    * | b9edde20 - cpu/microwatt: add io_regions and gcc_flags <Florent Kermarrec>
    * | 16e7c6b6 - cpu/microwatt: update copyright <Florent Kermarrec>
    * | 3d79324f - cpu/microwatt: drive stall signal (no burst support) <Florent Kermarrec>
    * | da3a178b - soc/cores/pwm: add clock_domain support <Florent Kermarrec>
    * | 9da28c4e - build/xilinx/XilinxMultiRegImpl: fix n=0 case <Florent Kermarrec>
    * | ec7dc2d8 - build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it) <Florent Kermarrec>
    * | 1b963bb2 - soc/cores/cpu: add initial Microwatt gateware support <Florent Kermarrec>
    * | c34255d2 - soc/cores/cpu/minerva: add self.reset to i_rst <Florent Kermarrec>
    * |   8b6f9e0a - Merge pull request timvideos#315 from gsomlo/gls-csr-assert <enjoy-digital>
    |\ \
    | * | a0dad1b0 - soc_core: additional CSR safety assertions <Gabriel Somlo>
    |/ /
    * | fb6b0786 - soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size) <Florent Kermarrec>
    * | b1a1e5e2 - soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin) <Florent Kermarrec>
    * | 061d593d - cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5) <Florent Kermarrec>
    * | a0122f98 - build/xilinx/vivado: move build_script generation <Florent Kermarrec>
    * | 18ff8f38 - build/xilinx/vivado: cleanup/simplify <Florent Kermarrec>
    * | 0931ccc9 - build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support) <Florent Kermarrec>
    * | b1b92053 - build/xilinx/common/platform/programmer: cleanup pass <Florent Kermarrec>
    * | edaa66bb - boards: add Lambdaconcept's PCIe Screamer (R02) <Florent Kermarrec>
    * | a8635c48 - targets/versa_ecp5: fix compilation with diamond <Florent Kermarrec>
    * | 30a18808 - boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals. <Florent Kermarrec>
    * | 23c33cfa - build: automatically add keep attribute to signals with timing constraints. <Florent Kermarrec>
    * | 4c9af635 - build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands <Florent Kermarrec>
    * | 22e6f5ac - build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed. <Florent Kermarrec>
    * | 8fb3f9a9 - build/lattice: cleanup/simplify (no functional changes) <Florent Kermarrec>
    * | 946478a7 - build/lattice: cleanup/simplify <Florent Kermarrec>
    * | 60edca23 - build/microsemi: cleanup/simplify (no functional change) <Florent Kermarrec>
    * | 50fdc5ce - build/altera: cleanup/simplify (no functional change) <Florent Kermarrec>
    * |   b17dfafa - Merge pull request timvideos#313 from mmicko/yosys_ise_flow_fix <Tim Ansell>
    |\ \
    | * | 783dfa50 - Properly select family for those currently supported <Miodrag Milanovic>
    | * | 6560911d - Integrate with latest yosys changes <Miodrag Milanovic>
    * | | 8d90f4e9 - build/xilinx/vivado: use VHDL 2008 as default <Florent Kermarrec>
    * | | cfd17321 - targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed) <Florent Kermarrec>
    * | | 201d60f3 - targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16) <Florent Kermarrec>
    * | | 6b820647 - targets: uniformize, improve presentation <Florent Kermarrec>
    * | | 718f6995 - README: fix LitePCIe Travis-CI link <Florent Kermarrec>
    * | | 6de20f18 - soc/interconnect/csr: add fields support for CSRStorage's write simulation method <Florent Kermarrec>
    * | | 2567a0ae - soc/cores/gpio: add GPIO Tristate <Florent Kermarrec>
    * | | d702c0fe - setup.py: update long_description <Florent Kermarrec>
    * | | c9665aed - README.md: use litex logo <Florent Kermarrec>
    * | | 82819dd5 - README: switch to Markdown <Florent Kermarrec>
    * | |   90f9ffc5 - Merge pull request timvideos#311 from kbeckmann/trellis_cabga256 <Tim Ansell>
    |\ \ \
    | |/ /
    |/| |
    | * | f411d6d3 - trellis: Support the CABGA256 package <Konrad Beckmann>
    |/ /
    * |   3d20442f - Merge pull request timvideos#310 from xobs/spi-flash-mode3-doc <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 581c2372 - spi_flash: correct documentation on SPI mode <Sean Cross>
    |/
    * de205d4a - tools/remote/comm_udp: only use one socket <Florent Kermarrec>
    * bdaca40f - build/generic_platform: avoid duplicate in GenericPlatform.sources <Florent Kermarrec>
    * 6883a436 - soc/cores/clock: change drp_locked to CSRStatus and connect it :) <Florent Kermarrec>
    * 36107cdf - soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal <Florent Kermarrec>
    *   e8e70b16 - Merge pull request timvideos#309 from antmicro/mmcm-fix <enjoy-digital>
    |\
    | * fd14b765 - soc/cores/clock: add lock reg and assign reset <Pawel Czarnecki>
    * 04017519 - soc/interconnect/axi: add Wishbone2AXILite <Florent Kermarrec>
    * 4b073a44 - test/test_axi: cosmetic <Florent Kermarrec>
    * d9055211 - build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository <Florent Kermarrec>

 * litex-renode changed from 70e884e to 2ed761f
    * 2ed761f - Update copyrights <Mateusz Holenko>
    *   d07cddb - Merge pull request timvideos#25 from antmicro/etherbone <Tim Ansell>
    |\
    | * 62b1406 - generate_renode_scripts: Generate etherbone bridge <Mateusz Holenko>
    | * eb6a2a4 - geneate_renode_scripts: Extract peripheral handlers <Mateusz Holenko>
    | * adc338e - generate_renode_scripts: Update copyrights <Mateusz Holenko>
    |/
    *   eab2fab - Merge pull request timvideos#24 from antmicro/cpu_type_detection <Tim Ansell>
    |\
    | * 986ddcf - generate-renode-scripts: rework cpu type detection <Mateusz Holenko>
    * |   f2d7987 - Merge pull request timvideos#23 from antmicro/flash_binary_labels <Tim Ansell>
    |\ \
    | |/
    |/|
    | * d2c7536 - Use constant from the config as flash binary offset <Mateusz Holenko>
    |/
    * 3997fff - Merge pull request timvideos#21 from antmicro/soc_controller <Tim Ansell>
    * ba983d7 - Add generation of LiteX SoC Controller <Mateusz Holenko>

 * migen changed from 0.6.dev-328-gd11565a to 0.6.dev-335-g3f9809b
    * 3f9809b - platforms: add zc706 + coraz7_07s <Astro>
    * e2e6c72 - sayma: sata -> fat_pipe <Sebastien Bourdeauducq>
    * 7a54c79 - metlino: add ddmtd_helper_clk <Sebastien Bourdeauducq>
    * 56e1b4e - metlino: add DCXO control signals <Sebastien Bourdeauducq>
    * 084e2a2 - metlino: add clock muxes <Sebastien Bourdeauducq>
    * 4d4d055 - metlino: add SFPs <Sebastien Bourdeauducq>
    * 2480d49 - metlino: fix clk200 <Sebastien Bourdeauducq>

 * nmigen changed from f207f3f to 57d95b7
    *   57d95b7 - Merge branch 'master' of https://github.com/nmigen/nmigen <Sebastien Bourdeauducq>
    |\
    | * dfcf793 - hdl.{ast,dsl}: allow whitespace in bit patterns. <whitequark>
    * | 7245b1e - Update README. <Sebastien Bourdeauducq>
    * | 60447a0 - Merge branch 'master' of https://github.com/nmigen/nmigen <Sebastien Bourdeauducq>
    |\|
    | * a295e35 - hdl.ast: update documentation for Signal. <whitequark>
    | * 49758a3 - hdl.ast: prohibit shifts by signed value. <whitequark>
    | * cce6b86 - build.plat: align pipeline with Fragment.prepare(). <whitequark>
    | * 6fd7cba - hdl.dsl: don't allow inheriting from Module. <whitequark>
    | * afece15 - hdl.ast: warn on unused property statements (Assert, Assume, etc). <whitequark>
    | * 9fb4a4f - _unused: extract must-use logic from hdl.ir. <whitequark>
    | * 687d3a3 - hdl.dsl: add missing case width check for Enum values. <whitequark>
    | * a9da9ef - README: clarify relationship to Migen. <whitequark>
    | * 9964fc6 - hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error. <whitequark>
    | * 3ac13eb - back.rtlil: don't emit wires for empty signals. <whitequark>
    | * b72c3fc - vendor.lattice_ecp5: support internal oscillator (OSCG). <Mike Walters>
    | * ec3a219 - build.dsl: allow strings to be used as connector numbers. <Jaro Habiger>
    | * 7792a6c - vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files <Sylvain Munaut>
    | * c280c7c - Update README. <whitequark>
    * | c42c3a0 - vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files <Sylvain Munaut>
    |/
    * a7be3b4 - hdl.ir: resolve hierarchy conflicts before creating missing domains. <whitequark>
    * 7cb3095 - hdl.xfrm: transform drivers as well in DomainRenamer. <whitequark>
    * e18385b - Remove everything deprecated in nmigen 0.1. <whitequark>
    * e4e2671 - Signal: allow to use integral Enum for reset value. <Staf Verhaegen>
    * 8184efd - vendor.intel: fix output enable width for XDR=0 case. <schwigi>
    * 63902dd - build.run: fix indentation. <Alain Péteut>
    * 476ce15 - back.rtlil: do not consider unreachable array elements when legalizing. <whitequark>
    * 318274d - hdl.mem: fix src_loc_at in ReadPort, WritePort. <whitequark>
    * 6765021 - hdl.ast: Fix width for unary minus operator on signed argument. <Marcin Kościelnicki>
    * 7650431 - back.pysim: fix miscompilation of Signal(unsigned) - Signal(signed). <whitequark>
    * d048f06 - hdl.ast: actually remove simulator commands. <whitequark>
    * 72cfdb0 - vendor.intel: silence meaningless warnings in nMigen files <Dan Ravensloft>
    * 7df7005 - back.pysim: redesign the simulator. <whitequark>
    * f8428ff - back.rtlil: infer bit width for instance parameters. <whitequark>
    * 56bb42a - hdl.ir: for instance ports, prioritize defs over uses. <whitequark>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (remotes/origin/HEAD)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (remotes/origin/HEAD)
 8fee3c7edfc5443ac8d1991d27e69c99072d7174 litedram (remotes/origin/HEAD)
 32d4af1148d59939fdf04b4ba319c83427b698c3 liteeth (remotes/origin/HEAD)
 10e520ed8476b04000122385e34f575629c4c6d6 litepcie (remotes/origin/HEAD)
 1e3573b07d382eac50ef764fd839009bf90cb8ce litesata (remotes/origin/HEAD)
 b3d1e6938f42045ade1fcb10aa2498722a4ea041 litescope (remotes/origin/HEAD)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 49d812694951a924617d8e429d72c0d4da96372a litevideo (remotes/origin/HEAD)
 9249fc90cf0f1a97c6960ae80cb167533ff75857 litex (remotes/origin/HEAD)
 2ed761f4c138f0237a7dca8d8dd45cea0b3c24d1 litex-renode (remotes/origin/HEAD)
 3f9809b0ea62b26f6c99f1b5221b22f8255bc1f6 migen (0.6.dev-335-g3f9809b)
 57d95b7f95dd37e2527db7b04be9ac8f324133e2 nmigen (v0.1-38-g57d95b7)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this issue Jun 2, 2020
@mateusz-holenko
Updating submodules.
a7145ef 
 * litedram changed from de55a8e to d62fd24
    *   d62fd24 - Merge pull request #201 from antmicro/jboc/spd-read <enjoy-digital>
    |\
    | * 4233f86 - modules/spd: save SPD data in SDRAMModule to allow for runtime verification <Jędrzej Boczar>
    * | f23cb80 - litedram_gen: revert builder.build(..., regular_comb=False). <Florent Kermarrec>
    * | d1db115 - litedram_gen: review/simplify #197. <Florent Kermarrec>
    * |   a8e281f - Merge pull request #197 from ozbenh/standalone-sim <enjoy-digital>
    |\ \
    | * | d0f0c94 - phy/model: Don't generate empty mem_*.init files <Benjamin Herrenschmidt>
    | * | b8d6da5 - gen: Allow generation of a standalone sim model <Benjamin Herrenschmidt>
    * | |   83b9a1d - Merge pull request #199 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \ \
    | |/ /
    |/| /
    | |/
    | * cbe91bc - modules: add function for parsing SPD EEPROM dumps from BIOS firmware <Jędrzej Boczar>
    * | 639a31f - test/test_timing: update test_txxd_controller. <Florent Kermarrec>
    * | 3c1ab76 - litedram/common/tXXDController: only set reset to 1 when txxd is None. <Florent Kermarrec>
    |/
    *   e95af3f - Merge pull request #195 from enjoy-digital/bios-libs <enjoy-digital>
    |\
    | * fe48a92 - test/reference: update. <Florent Kermarrec>
    | * c30910a - init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS. <Florent Kermarrec>
    |/
    * 5078b19 - core/crossbar: remove retro-compat > 6 months old. <Florent Kermarrec>
    * 3b105d5 - modules: fix SDRAMRegisteredModule. <Florent Kermarrec>
    *   b2a5685 - Merge pull request #189 from daveshah1/ddr4_rdimm_init <enjoy-digital>
    |\
    | * 70054ba - Add support for DDR4 RDIMMs <David Shah>
    * | 7ae4ad5 - modules: add SDR/DDR/DDR2/DDR3/DDR4 SDRAMModule (and Registered versions). <Florent Kermarrec>
    * | 1f7d9eb - litedram_gen: pass FPGA speedgrade to iodelay_pll. <Florent Kermarrec>
    * | f4871b9 - litedram_gen: use default settings on wb_bus. <Florent Kermarrec>
    * | 6fb8396 - litedram_gen: remove csr_base (no longer needed since CPUNone type will automatically set csr mapping to 0x00000000) and create a use bus with the same address_width as the main bus of the SoC. <Florent Kermarrec>
    * | 94c215e - litedram_gen: review/simplify #193, always add ddrctrl. <Florent Kermarrec>
    * |   f036ec2 - Merge pull request #193 from ozbenh/standalone-cores <enjoy-digital>
    |\ \
    | * | 04717b4 - gen: Rename standalone core wishbone <Benjamin Herrenschmidt>
    | * | b0838f7 - gen: Add option to specify CSR alignment <Benjamin Herrenschmidt>
    | * | d5a03b3 - gen: Add option to generate DDRCTL on standalone cores <Benjamin Herrenschmidt>
    | * | efad6b3 - gen: Add option to specify CSR base for standalone cores <Benjamin Herrenschmidt>
    | * | c91cbb5 - gen: Remove obsolete bus_expose config option <Benjamin Herrenschmidt>
    |/ /
    * | 4e539ad - litedram_gen: switch to SoCCore. <Florent Kermarrec>
    * | ac33d29 - litedram_gen: simplify and expose bus when CPU is set to None. <Florent Kermarrec>
    * | fe47838 - litedram_gen: expose a Bus Slave port instead of a CSR port. <Florent Kermarrec>
    * | 52b49fb - test/reference: update. <Florent Kermarrec>
    * | 52ca393 - modules: add MT41J512M16/MT41K512M16. <Florent Kermarrec>
    * | 589957f - phy: extend Bitslip capability to 2 sys_clk cycles. <Florent Kermarrec>
    * | 5c0231d - common/BitSlip: add cycles parameter to extend bitstlip to multiple system clock cycles. <Florent Kermarrec>
    * | ed0810a - gen: Optionally pass cpu_variant from YAML to SoC <Benjamin Herrenschmidt>
    |/
    *   dfe6f90 - Merge pull request #188 from daveshah1/ddr4_dimm_x4 <enjoy-digital>
    |\
    | * 5b4381b - usddrphy: Support for x4 chip based DIMMs <David Shah>
    * |   9f136c0 - Merge pull request #187 from daveshah1/add_MTA18ASF2G72PZ <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 97f0a37 - modules: Add MTA18ASF2G72PZ DDR4 RDIMM <David Shah>
    |/
    * 9a2d3f0 - common: add PHYPadsReducer to only use specific DRAM modules. <Florent Kermarrec>
    * 20a849c - test/reference: update ddr4_init.h <Florent Kermarrec>
    *   cec3a99 - Merge pull request #181 from antmicro/jboc/eeprom-timings <enjoy-digital>
    |\
    | * 312bce2 - modules: pass rate automatically when creating module from SPD data <Jędrzej Boczar>
    | * 07bbd79 - modules: update existsing SO-DIMM timings based on SPD data <Jędrzej Boczar>
    | * cf83ac6 - test: improve SPD tests of Micron DDR3 SO-DIMM modules <Jędrzej Boczar>
    | * 854a614 - modules: fix calculations of speedgrade from tck in SPD data <Jędrzej Boczar>
    | * c744204 - modules: fix nrows in MT8KTF51264 <Jędrzej Boczar>
    | * 3980e06 - modules: add option to load module parameters from SPD data <Jędrzej Boczar>
    * | 48c2fc2 - phy: simplify/improve dqs preamble/postamble. <Florent Kermarrec>
    * | eaf0691 - phy/ecp5ddrphy: simplify, working with dqs preamble/postamble. <Florent Kermarrec>
    * | 12a017f - phy/ecp5ddrphy: simplify/cleanup. <Florent Kermarrec>
    * | 62915cd - phy: rework BitSlip to simplify integration, add DQSPattern module. <Florent Kermarrec>
    * | 9ff9e82 - phy/usddrphy: move pads.ten control to control block. <Florent Kermarrec>
    * | 91a9a2a - phy/ecp5ddrphy: fix dqs preamble/postamble control. (make it similar to 7-series/Ultrascale). <Florent Kermarrec>
    * | 5d29686 - phy/s7ddrphy/usddrphy: more compact write dqs postamble/preamble control path. <Florent Kermarrec>
    * | 8d0e7f6 - phy/usddrphy: simplify/cleanup write control path/dqs postamble/preamble control path. <Florent Kermarrec>
    * | 57b16c2 - phy/usddrphy: simplify/cleanup write control path, add DQS Pre/Postamble support. <Florent Kermarrec>
    * | 1462a43 - phy/usddrphy: cleanup/simplify read control path. <Florent Kermarrec>
    * | cd671f9 - phy/s7ddrphy: cleanup/simplify read control path. <Florent Kermarrec>
    * | d061e60 - test/reference: update. <Florent Kermarrec>
    * | 45a03df - phy/init: add phytype to PhySettings and export more parameters to C header to simplify software. <Florent Kermarrec>
    * | 2df9004 - init: improve ident. <Florent Kermarrec>
    * | eca7fc2 - phy/ecp5ddrphy: remove Bitslip from comment (no longer present). <Florent Kermarrec>
    * | f4f2948 - phy/ecpddrphy: remove Bitslip (not used and redundant with dqs_read) and use BitSlip software control to move dqs_read. <Florent Kermarrec>
    * | e2b4c2b - phy/ecp5ddrphy: cosmetics. <Florent Kermarrec>
    |/
    * f68f1dd - phy/ecp5ddrphy/control: cleanup/simplify and document (no functional changes). <Florent Kermarrec>
    * fdf7c76 - phy/control: cleanup/simplify (no functional changes). <Florent Kermarrec>
    * a767618 - phy: improve flow control readability (add separators between Read/Write/Write DQS Postamble/Preamble parts). <Florent Kermarrec>

 * liteeth changed from 705003e to 0feed17
    * 0feed17 - phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work). <Florent Kermarrec>
    * 53c9eb9 - core/ip: move mcase_oui/ip_mask definition to common and set target_mac with NextValue. <Florent Kermarrec>
    *   58e1681 - Merge pull request #41 from shuffle2/mcast <enjoy-digital>
    |\
    | * 6d00ec1 - iptx: support multicast mac and bypass arp table <Shawn Hoffman>
    * | 8afdec9 - phy/ecp5rgmii: review/simplify inband_status integration. <Florent Kermarrec>
    * |   55af430 - Merge pull request #40 from shuffle2/master <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 26c4e41 - ecp5rgmii: enable reading inband PHY_status <Shawn Hoffman>
    |/
    * dc67e6d - phy/ecp5rgmii: use DDROutput/DDRInput now available for ECP5. <Florent Kermarrec>

 * litepcie changed from 586ef78 to b0e8383
    * b0e8383 - frontend/dma/LitePCIeDMAReader: immediately return to IDLE state when disabled. <Florent Kermarrec>
    *   4e333cb - Merge pull request #29 from sergachev/master <enjoy-digital>
    |\
    | * 8192494 - kernel: remove unnecessary call to pci_release_regions() on device remove <Ilia Sergachev>
    |/
    * c2fd143 - phy/s7pciephy: expose disable_constraints parameter to use_external_hard_ip. <Florent Kermarrec>
    * 6049a69 - litepcie_gen: add optional Sphinx/Html doc generation with --doc. <Florent Kermarrec>
    * 6bb89af - phy/s7pciehy: disable constraints generated from the .xci and use our owns. <Florent Kermarrec>
    *   ef7d40e - Merge pull request #28 from sergachev/master <enjoy-digital>
    |\
    | * 3eb2b86 - test_dma: remove unused imports and variables, fix mistypes <Ilia Sergachev>
    |/
    *   9a3ada5 - Merge pull request #27 from sergachev/master <enjoy-digital>
    |\
    | * e637090 - dma: fix another couple of mistypes <Ilia Sergachev>
    | * 4c4e3bf - dma: fix mistypes in comments <Ilia Sergachev>
    |/
    * 3ca6e38 - frontend/dma/monitor: reduce count_width from 32-bit (default) to 16-bit. <Florent Kermarrec>
    * 22faa07 - litepcie_gen: add pcie_data_width support. <Florent Kermarrec>
    *   96a6cdc - Merge pull request #25 from sergachev/master <enjoy-digital>
    |\
    | * 5804b43 - software: fix definitions <Ilia Sergachev>
    * 0496daf - litepcie_gen: add buffers on DMA sink/source to ensure data are clocked on LitePCIe interface and ease integration. <Florent Kermarrec>
    * 7818ace - frontend/dma: fix level CSRStatus size (+1). <Florent Kermarrec>
    * a85b1d7 - tlp/controller: expose cmp_bufs_buffered parameter. <Florent Kermarrec>
    * 264d7f3 - frontend/dma: allow asymetric writer/reader buffering depths. <Florent Kermarrec>
    * 9cb938e - frontend/dma: expose table_depth parameter. <Florent Kermarrec>
    * a6d836e - gen/examples: add software reset. <Florent Kermarrec>

 * litex changed from 2d018826 to 77139289
    *   77139289 - Merge pull request #552 from ozbenh/memspeed-long <Tim Ansell>
    |\
    | * 6239eac1 - sdram: Use unsigned long for memory test <Benjamin Herrenschmidt>
    * |   a116578c - Merge pull request #550 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \
    | * | a433c837 - bios/litedram: add option to verify SPD EEPROM memory contents <Jędrzej Boczar>
    | * | 1692dfbf - build/sim/spdeeprom: use hex format when loading from file <Jędrzej Boczar>
    * | |   b98a9192 - Merge pull request #549 from antmicro/mglb/fix-vivado-yosys <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | a4e83234 - build/xilinx: do not assume build name is "top" <Mariusz Glebocki>
    |/ /
    * |   5cc7a988 - Merge pull request #547 from gsomlo/gls-fix-sdcard-status <enjoy-digital>
    |\ \
    | * | 28290efd - soc/software/litesdcard: update for response register back to 128 bits <Gabriel Somlo>
    * | | 395af900 - interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify. <Florent Kermarrec>
    * | | 511832a9 - soc/interconnect/axi: generate wishbone.sel for reads. <Florent Kermarrec>
    * | | 4f82a36a - soc/software: only keep 32-bit CSR alignment support. <Florent Kermarrec>
    |/ /
    * | 75936775 - wishbone/wishbone2csr: use wishbone.sel on CSR write. <Florent Kermarrec>
    * | b1ec092e - soc/software/litesdcard: use new send register to send command and remove CSR8_CMD_FIX. <Florent Kermarrec>
    * | efcba14b - platforms/nexys_video: add spisdcard pins. <Florent Kermarrec>
    * | 119ce56f - targets/nexys_video: add spi-sdcard and sdcard support. <Florent Kermarrec>
    * | cc595017 - plaforms/nexys_video: keep up to date with litex-boards. <Florent Kermarrec>
    * | 5cc564fb - targets: simplify Ethernet/Etherbone integration on targets with both. <Florent Kermarrec>
    * | 55c7461e - bios/cmds/cmd_litesdcard: rewrite comments/descriptions. <Florent Kermarrec>
    * | 6cb03963 - bios/main: replace / with -. <Florent Kermarrec>
    * |   5dd5f97b - Merge pull request #545 from gsomlo/gls-fix-mmptr <enjoy-digital>
    |\ \
    | * | 3e1b17d4 - csr: fix simple accessor alignment <Gabriel Somlo>
    * | | 6c1e2d84 - software/liblitesdcard: replace hexdump with dump_bytes already available in the BIOS. <Florent Kermarrec>
    |/ /
    * | 9e068a74 - soc/add_sdcard: add with_emulator parameter to use SDCard emulator (from Google Project Vault) and integrate it in litex_sim. <Florent Kermarrec>
    * | 2ae55e80 - setup.py: add litex_jtag_uart and litex_crossover_uart to console_scripts. <Florent Kermarrec>
    * | 62d939e8 - Merge pull request #543 from antmicro/jboc/eeprom-sim <enjoy-digital>
    |\|
    | * a0ce4ce5 - litex/build/sim: add module for simulating SPD EEPROM <Jędrzej Boczar>
    * | c4f96318 - targets/nexys4ddr: fix sdcard assert. <Florent Kermarrec>
    * | 76cc112e - bios: add main bus and csr bus infos, use KiB/GiB. <Florent Kermarrec>
    |/
    * 02072dea - integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically. <Florent Kermarrec>
    * 4b3afa75 - integration/soc: add add_sdcard method with integration code from nexys4ddr. <Florent Kermarrec>
    * c78caeb9 - csr: Fix definition(s) of CSR_BASE in generated headers <Benjamin Herrenschmidt>
    * f8bb500a - liblitedram/sdram: Add option to disable cdelay() <Benjamin Herrenschmidt>
    * 6d72ef28 - cpu/serv: add variants. <Florent Kermarrec>
    * fd7ec50e - soc/integration/export: add optional csr_base parameter. <Florent Kermarrec>
    * 795ff08a - build/sim/verilator: add regular_comb parameter (that defaults to False) and pass it to get_verilog. <Florent Kermarrec>
    *   25d2e7c9 - Merge pull request #542 from gsomlo/gls-sdcard-followup <enjoy-digital>
    |\
    | * 6da98ca1 - software/bios: fixup sdclk command <Gabriel Somlo>
    * |   3fd6ecd8 - Merge pull request #541 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \
    | * | 1172c10a - bios: move I2C from liblitedram to libbase <Jędrzej Boczar>
    | * | 472bf9ac - bios/sdram: expose I2C functions <Jędrzej Boczar>
    | * | bdc7eb5c - litex_sim: load SPD data from files in hexdump format as printed in BIOS <Jędrzej Boczar>
    | * | a42dc974 - bios/sdram: add BIOS command for reading SPD <Jędrzej Boczar>
    | * | 8fd3e74e - bios/sdram: add firmware for reading SPD EEPROM <Jędrzej Boczar>
    * | | 68f83cbc - CHANGES: document deprecated/moved modules. <Florent Kermarrec>
    * | | ab806060 - soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone. <Florent Kermarrec>
    * | | 0a3d649a - interconnect/wishbone: integrate Wishbone2CSR. <Florent Kermarrec>
    * | | b5b88d27 - interconnect/csr_bus: add separators. <Florent Kermarrec>
    * | | 86952a6e - interconnect/wishbone: remove CSRBank (probably not used by anyone). <Florent Kermarrec>
    * | | e404608c - interconnect/wishbone: add separators and move SDRAM/Cache. <Florent Kermarrec>
    * | | 1fddd0e3 - interconnect/wishbone: simplify DownConverter. <Florent Kermarrec>
    * | | e0d26820 - interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten). <Florent Kermarrec>
    | |/
    |/|
    * | 696b31ed - tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM. <Florent Kermarrec>
    * | 2efcf879 - targets/nexys4ddr: update add_sdcard method. <Florent Kermarrec>
    * | 2934c085 - CHANGES: add JTAG UART. <Florent Kermarrec>
    * | 3b47d4a4 - tools/litex_jtag_uart: add openocd config and telnet port parameters. <Florent Kermarrec>
    * | 67cf6703 - cpus: remove common cpu variants/extensions definition and simplify variant check. <Florent Kermarrec>
    * | 062ff67e - cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin. <Florent Kermarrec>
    * | 24687cbd - tools/litex_client/RemoteClient: add base_address parameter. <Florent Kermarrec>
    * | 78a9579e - cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word. <Florent Kermarrec>
    * |   370e4652 - Merge pull request #539 from dayjaby/pr-fix_uart_startbit <enjoy-digital>
    |\ \
    | * | e853ad4b - fix uart startbit: 1 cycle later <David Jablonski>
    * | | c75cf45a - tools: add litex_jtag_uart to create a virtual uart for the jtag uart. <Florent Kermarrec>
    * | | 2cf83b9f - tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now. <Florent Kermarrec>
    * | | bed5aafd - tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...). <Florent Kermarrec>
    * | | 3833bc3e - litex_sim: override uart_name to sim only for serial. <Florent Kermarrec>
    * | | da7fd308 - CHANGES: update. <Florent Kermarrec>
    * | | 2fb52e66 - integration/soc: remove TODO in header. <Florent Kermarrec>
    * | | b65f18c3 - cpu/cv32e40p: fix copyright year. <Florent Kermarrec>
    * | | 30f35170 - cpu/cv32e40p: add copyright and improve indentation. <Florent Kermarrec>
    * | | b23702ec - litex_setup/pythondata-cpu-cv32e40p: clone in recursive mode. <Florent Kermarrec>
    * | |   4c4cd335 - Merge pull request #535 from antmicro/arty-cv32e40p <enjoy-digital>
    |\ \ \
    | * | | 2d6ee5aa - cores/cpu: add cv32e40p <Piotr Binkowski>
    | * | | ca8cb834 - software/bios/isr: add support for cv32e40p <Piotr Binkowski>
    | * | | 2903b1bf - litex_setup: add pythondata for cv32e40p <Piotr Binkowski>
    * | | |   7d09ea19 - Merge pull request #538 from antmicro/fix_libbase <enjoy-digital>
    |\ \ \ \
    | * | | | 9d16b0fc - libbase: Include missing uart header <Mateusz Hołenko>
    |/ / / /
    * | | | 3d06dc02 - test/test_targets: update build_test. <Florent Kermarrec>
    * | | | 42350f6d - platforms/targets: keep in sync with litex-boards. <Florent Kermarrec>
    * | | | 2eea7864 - build/sim: rename dut to sim (for consistency with other builds). <Florent Kermarrec>
    * | | | a6cbbc9d - integration/soc: set build_name to platform.name when not specified. <Florent Kermarrec>
    * | | | 16417cb8 - software/liblitespi: fix #endif location. <Florent Kermarrec>
    * | | |   9bdb063b - Merge pull request #516 from antmicro/i2s_support_arty <enjoy-digital>
    |\ \ \ \
    | * | | | ce499900 - Extend I2S capabilities <Pawel Sagan>
    * | | | |   c2e9a26e - Merge pull request #534 from fjullien/fix_litex_sim_warn <enjoy-digital>
    |\ \ \ \ \
    | |/ / / /
    |/| | | |
    | * | | | 7c5f56c2 - litex/sim: fix compiler warnings <Franck Jullien>
    |/ / / /
    * | | |   6fedaa70 - Merge pull request #533 from antmicro/fix-dummy-bits-function-name <enjoy-digital>
    |\ \ \ \
    | * | | | ab41e27e - software/liblitespi/spiflash: fix dummy bits setup function name <Jan Kowalewski>
    |/ / / /
    * | | | d71152ef - litex_setup: move requests import to avoid having to install it on travis. <Florent Kermarrec>
    * | | | 9854fdd5 - .travis: install  requests package before running litex_setup.py. <Florent Kermarrec>
    * | | | bd0f21ba - targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets). <Florent Kermarrec>
    * | | | 80eca300 - software/liblitespi/spiflash: review/simplify/update and test on arty. <Florent Kermarrec>
    * | | | 4a175620 - build/xilinx: simplify LITEX_ENV_ISE/VIVADO handling. <Florent Kermarrec>
    * | | | e91c3171 - software/bios: cleanup includes and specify the lib in the include. <Florent Kermarrec>
    * | | | c3a03d0d - software: create liblitespi and mode litespi code to it (with some parts commented out for now). <Florent Kermarrec>
    * | | | 61238bee - soc/software/bios: add autoconfiguration functionality for LiteSPI core <Jan Kowalewski>
    * | | | d3890055 - litex_setup: add automatic update of litex_setup (because it also changes) and be sure we are on master branch before update. <Florent Kermarrec>
    * | | |   939f546a - Merge pull request #531 from gsomlo/gls-bios-linker <enjoy-digital>
    |\ \ \ \
    | |_|/ /
    |/| | |
    | * | | c5524dbf - software/bios: fix link order to avoid undefined symbol errors <Gabriel Somlo>
    |/ / /
    * | | b4267a79 - build/xilinx: source settings64.sh automatically just before build if LITEX_ENV_ISE/LITEX_ENV_VIVADO environment variables are set. <Florent Kermarrec>
    * | | de7e0ee9 - integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed. <Florent Kermarrec>
    * | | 6f8f0d23 - litex_setup: add litehyperbus and remove hyperbus core/test. <Florent Kermarrec>
    |/ /
    * | 109fd267 - integration/builder: simplify default output_dir to "build/platform". <Florent Kermarrec>
    * | 55c0ddab - litex_setup: add sha1 support on git clone/pull and fix microwatt to a specific sha1. <Florent Kermarrec>
    |/
    *   23d43a2c - Merge pull request #530 from enjoy-digital/bios-libs <enjoy-digital>
    |\
    | * 7192397a - software/libbase: remove linker-sdram (unused). <Florent Kermarrec>
    | * b4b84def - software/bios: mode spisdcard code to liblitesdcard. <Florent Kermarrec>
    | * 21e2a34c - software/bios: rename commands to cmds and update with libs' names. <Florent Kermarrec>
    | * 33f6ce74 - software/bios: move hw flags definitions to respective libs, remove hw/flags.h. <Florent Kermarrec>
    | * 403355a8 - software: create liblitescard and move sdcard init/test code to it. <Florent Kermarrec>
    | * 920d0ee5 - software: create liblitedram and move sdram init/test code to it. <Florent Kermarrec>
    | * c95084e5 - bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash. <Florent Kermarrec>
    | * 573a8815 - software/bios/commands: rename cmd_mdio to cmd_liteeth. <Florent Kermarrec>
    | * ff8d9e61 - software/bios: move mdio to libliteeth. <Florent Kermarrec>
    | * 70a67ce7 - software/bios: rename libnet to libliteeth and move all ethernet files to it. <Florent Kermarrec>
    | * 56b8723b - software/bios: rename cmd_mem_access to cmd_mem. <Florent Kermarrec>
    |/
    * a02077d5 - cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build. <Florent Kermarrec>
    * b5352f40 - cpu/microwatt: update microwatt_wraper.vhdl <Florent Kermarrec>
    * be25500e - uptime: rework and integrate it in Timer to ease software support. <Florent Kermarrec>
    * d6549ff8 - bios: add uptime command and rewrite cmd_bios comments. <Florent Kermarrec>
    * fc0e55be - soc: improve uptime comments. <Florent Kermarrec>
    *   840679ad - Merge pull request #526 from rprinz08/master <enjoy-digital>
    |\
    | * 3f649077 - Make booting from SD-Card to behave same as from SPI flash <rprinz08>
    * | 82364de5 - soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled. <Florent Kermarrec>
    |/
    * 3391398a - bios/sdram: always show bitslip on two digits to keep scan aligned. <Florent Kermarrec>
    *   4a5072a0 - Merge pull request #517 from ozbenh/csr-access-rework <enjoy-digital>
    |\
    | * 1e35b0e7 - csr: Rework accessors <Benjamin Herrenschmidt>
    |/
    * d4f44597 - CHANGES: update. <Florent Kermarrec>
    *   a51c7a7b - Merge pull request #518 from enjoy-digital/csr_base <enjoy-digital>
    |\
    | * 748ef1ad - export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses. <Florent Kermarrec>
    * |   177c1e53 - Merge pull request #523 from DurandA/patch-5 <enjoy-digital>
    |\ \
    | * | 9d9e7d54 - Update litex_term help <Arnaud Durand>
    |/ /
    * | 2e59dc32 - platforms/nexys4ddr: add card detect pin to sdcard. <Florent Kermarrec>
    * | 51742be2 - integration/soc: review/simplify interconnect and add logger.info. <Florent Kermarrec>
    * |   78413cc0 - Merge pull request #519 from ozbenh/point2point <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 1ed68691 - soc: Revive generation of a PointToPoint interconnect <Benjamin Herrenschmidt>
    |/
    * 9f941138 - test/test_targets: workaround to fix travis. <Florent Kermarrec>
    * 9d1443c1 - cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that. <Florent Kermarrec>
    * 5ea3bae0 - bios/boot: review/fix #503. <Florent Kermarrec>
    *   bf7857f5 - Merge pull request #503 from rprinz08/master <enjoy-digital>
    |\
    | * 1f55fcf4 - fixed bug in BIOS spi flash "fw" command <rprinz08>
    | * f062c0c4 - removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram <rprinz08>
    | * ea232fc5 - BIOS boot firmware from SPI with address offset <rprinz08>
    * |   b4e349eb - Merge pull request #513 from mubes/bios_linker <enjoy-digital>
    |\ \
    | * | d2d82dac - Bios linker edits to prevent inappropriate optimisation <Dave Marples>
    |/ /
    * | 3fb99b7d - cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite. <Florent Kermarrec>
    * |   2a5a7536 - Merge pull request #478 from antmicro/extended_spi_flash <enjoy-digital>
    |\ \
    | * | 00f973ea - spi_flash: extend non-bitbanged flash support <Jakub Cebulski>
    | * | a344e20b - spi_flash: fix building without bitbang <Jakub Cebulski>
    * | |   7d79da8e - Merge pull request #510 from mubes/colorlight_usb <enjoy-digital>
    |\ \ \
    | * | | 84997332 - Fix dumb missing line <Dave Marples>
    | * | |   33e202ed - Bring into line with master <Dave Marples>
    | |\ \ \
    | * | | | dc1d4520 - Addition of boot address parameter for trellis builds <Dave Marples>
    * | | | | 3a6dd95d - integration/soc: review/simplify changes for standalone cores. <Florent Kermarrec>
    * | | | |   0d5eb133 - Merge pull request #511 from ozbenh/standalone-cores <enjoy-digital>
    |\ \ \ \ \
    | * | | | | f628ff6b - WB2CSR: Use CSR address_width for the wishbone bus <Benjamin Herrenschmidt>
    | * | | | | 520c17e9 - soc_core: Add option to override CSR base <Benjamin Herrenschmidt>
    | * | | | | ecbd4028 - soc: Don't update CSR alignment when there is no CPU <Benjamin Herrenschmidt>
    | * | | | | f28f2471 - soc: Don't create a wishbone slave to LiteDRAM with no CPU <Benjamin Herrenschmidt>
    | * | | | | dcc881db - soc: Don't create a share intercon with only one master and one slave <Benjamin Herrenschmidt>
    | | |/ / /
    | |/| | |
    * | | | | 873d95e5 - interconnect/wishbonebridge: refresh/simplify. <Florent Kermarrec>
    * | | | |   c136113a - Merge pull request #506 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \ \ \
    | * | | | | aed1d514 - Update README.md and core.py for BlackParrot <sadullah>
    | * | | | | 5e4a4360 - Vivado Command Update for Systemverilog <sadullah>
    | |/ / / /
    * | | | |   d2c9d385 - Merge pull request #508 from antmicro/update_litesdcard <enjoy-digital>
    |\ \ \ \ \
    | |/ / / /
    |/| | | |
    | * | | | 0db35069 - Update Litex bios to handle updated litesdcard. <Kamil Rakoczy>
    |/ / / /
    * | | |   3ce90100 - Merge pull request #505 from DurandA/patch-3 <enjoy-digital>
    |\ \ \ \
    | * | | | 2c40967b - Enable 1x mode on SPI flash <Arnaud Durand>
    | | |_|/
    | |/| |
    * | | | e2176cef - soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters. <Florent Kermarrec>
    * | | | 1e610600 - build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends. <Florent Kermarrec>
    * | | |   ebcf67c1 - Merge pull request #502 from shuffle2/master <enjoy-digital>
    |\ \ \ \
    | * | | | eeee179d - diamond: close project when done <Shawn Hoffman>
    | * | | | 9b782bd7 - diamond: clock constraint improvements <Shawn Hoffman>
    | |/ / /
    * | | |   80f5327e - Merge pull request #490 from daveshah1/rdimm_bside_init <enjoy-digital>
    |\ \ \ \
    | * \ \ \   13db89eb - Merge branch 'master' into rdimm_bside_init <enjoy-digital>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | c9e36d7f - lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args. <Florent Kermarrec>
    * | | | | ea7fe383 - lattice/trellis: simplify seed support and add it to trellis_args. <Florent Kermarrec>
    * | | | |   5ee01c94 - Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed <enjoy-digital>
    |\ \ \ \ \
    | * | | | | ac1e9683 - Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs` <Ilya Epifanov>
    * | | | | |   5987ddb4 - Merge pull request #485 from ilya-epifanov/cpu-imac-config-for-vexriscv <enjoy-digital>
    |\ \ \ \ \ \
    | * \ \ \ \ \   c5f74a5a - Merge branch 'master' into cpu-imac-config-for-vexriscv <enjoy-digital>
    | |\ \ \ \ \ \
    | |/ / / / / /
    |/| | | | | |
    * | | | | | | 59d88a88 - integration/soc/add_adapter: rename is_master to direction. <Florent Kermarrec>
    * | | | | | |   57390666 - Merge pull request #504 from sergachev/master <enjoy-digital>
    |\ \ \ \ \ \ \
    | * | | | | | | e4fa4bbc - integration/soc: fix add_adapter for slaves <Ilia Sergachev>
    |/ / / / / / /
    * | | | / / / 2d70220b - bios: Fix warning on 64-bit <Benjamin Herrenschmidt>
    | |_|_|/ / /
    |/| | | | |
    * | | | | | fbbbdf03 - core/led: simplify LedChaser (to have the same user interface than GPIOOut). <Florent Kermarrec>
    * | | | | | 05869beb - cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :)) <Florent Kermarrec>
    * | | | | | 90c485fc - integration/soc: add clock_domain parameter to add_etherbone. <Florent Kermarrec>
    * | | | | | f1a50a21 - integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge). <Florent Kermarrec>
    | |_|_|/ /
    |/| | | |
    * | | | | 79ee135f - bios/sdram: fix lfsr typo. <Florent Kermarrec>
    * | | | |   162d3260 - Merge pull request #500 from mubes/fixups <enjoy-digital>
    |\ \ \ \ \
    | * \ \ \ \   2a37b97d - Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups <Dave Marples>
    | |\ \ \ \ \
    | * | | | | | 967e38bb - Small fixups to address compiler warnings etc. <Dave Marples>
    | | |_|_|_|/
    | |/| | | |
    * | | | | | d74f8fc9 - build/xilinx: add disable_constraints parameter to Platform.add_ip. <Florent Kermarrec>
    | |/ / / /
    |/| | | |
    * | | | | 84841e1d - bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt). <Florent Kermarrec>
    * | | | | 99c5b0fc - bios/sdram: Use an LFSR to speed up pseudo-random number generation <Benjamin Herrenschmidt>
    * | | | |   34f26868 - Merge pull request #499 from DurandA/patch-2 <enjoy-digital>
    |\ \ \ \ \
    | * | | | | 5e049d89 - Add data dirs to manifest <Arnaud Durand>
    * | | | | | 8b9aa16d - boards/platforms: update xilinx programmers. <Florent Kermarrec>
    * | | | | | 3c34039b - build/xilinx/vivado: ensure Vivado process our .xdc early. <Florent Kermarrec>
    |/ / / / /
    * | | | | b0578580 - gen/fhdl/verilog: explicitly define input/output/inout wires. <Florent Kermarrec>
    * | | | | 0aa3c339 - targets/genesys2: set cmd_latency to 1. <Florent Kermarrec>
    * | | | | 95b57899 - bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases). <Florent Kermarrec>
    * | | | | 98d1b451 - platforms/targets: fix CI. <Florent Kermarrec>
    * | | | | 22bcbec0 - boards: keep in sync with LiteX-Boards, integrate improvements. <Florent Kermarrec>
    * | | | | 28f85c74 - build/lattice/programmer: add UJProg (for ULX3S). <Florent Kermarrec>
    * | | | | 85ac5ef1 - build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer. <Florent Kermarrec>
    * | | | | 9a7f9cb8 - build/generic_programmer: catch 404 not found when downloading config/proxy. <Florent Kermarrec>
    * | | | | d0b8daa0 - build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request. <Florent Kermarrec>
    * | | | | b8f9f83a - build/openocd: add find_config method to allow using local config file or download it if not available locally. <Florent Kermarrec>
    * | | | | 9bef218a - cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt). <Florent Kermarrec>
    * | | | |   6f24d46d - Merge pull request #496 from gsomlo/gls-fix-makefiles <enjoy-digital>
    |\ \ \ \ \
    | * | | | | edfed4f0 - software/*/Makefile: no need to copy .S files from CPU directory <Gabriel Somlo>
    |/ / / / /
    * | | | |   7f8e34c6 - Merge pull request #494 from shuffle2/patch-2 <enjoy-digital>
    |\ \ \ \ \
    | * | | | | ee413527 - diamond: quiet warning about missing clkin freq for EHXPLLL <shuffle2>
    |/ / / / /
    * | | | | 07e0153b - CHANGES: update. <Florent Kermarrec>
    * | | | | 21127031 - cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple. <Florent Kermarrec>
    * | | | | c06a1279 - cpu/microwatt: add pythondata and fix build with it. <Florent Kermarrec>
    * | | | | 45377d9f - cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width. <Florent Kermarrec>
    * | | | | 7c69a6db - bios/cmd_mdio.c:  fix missing <base/mdio.h> import. <Florent Kermarrec>
    * | | | | b0205335 - cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c. <Florent Kermarrec>
    * | | | | 97e534d0 - cpus: add nop instruction and use it to simplify the BIOS. <Florent Kermarrec>
    * | | | | 4efc7835 - cpus: add human_name attribute and use it to simplify the BIOS. <Florent Kermarrec>
    * | | | | d81f171c - software/libbase/system.c: remove unused includes. <Florent Kermarrec>
    * | | | |   3bbadb35 - Merge pull request #492 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \ \ \
    | * \ \ \ \   999b93af - Merge branch 'master' into blackparrot_litex <enjoy-digital>
    | |\ \ \ \ \
    | |/ / / / /
    |/| | | | |
    * | | | | |   705d3887 - Merge pull request #474 from fjullien/term_hist_auto_compl <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | 74dc444b - bios: add auto completion for commands <Franck Jullien>
    | * | | | | | fc2b8226 - bios: switch command handler to a modular format <Franck Jullien>
    | * | | | | | 86cab3d3 - bios: move helper functions to their own file <Franck Jullien>
    | * | | | | | bc5a1986 - bios: add terminal history <Franck Jullien>
    | * | | | | | e764eabd - builder: add a parameter to pass options to BIOS Makefile <Franck Jullien>
    | | * | | | | 0c770e06 - Update README.md <Sadullah Canakci>
    | | * | | | | 19bb1b9b - update to comply with python-data layout <sadullah>
    | | * | | | | 3eb9efd6 - BP fpga recent version <sadullah>
    | | * | | | | bf864d33 - Fix memory transducer bug, --with-sdram for BIOS works, memspeed works <sadullah>
    | | * | | | | cf01ea65 - rebased, minor changes in core.py <sadullah>
    | | * | | | | b7b9a1f0 - Linux works, LiteDRAM works (need cleaning, temporary push) <sadullah>
    | | * | | | | 74140587 - Create GETTING STARTED <Sadullah Canakci>
    | |/ / / / /
    |/| | | | |
    * | | | | |   e853cac6 - Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | a11f1c39 - Removed erase flag and made progress output less noisy <Ilya Epifanov>
    | | |_|_|/ /
    | |/| | | |
    * | | | | |   a6779b9d - Merge pull request #491 from gsomlo/gls-spisd-clusters <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | c8e3bba4 - software: spisdcard: cosmetic: avoid filling screen with cluster numbers <Gabriel Somlo>
    * | | | | | | b5978b21 - .travis.yml: disable python3.5 test (nMigen requires 3.6+). <Florent Kermarrec>
    * | | | | | | 10371a33 - CHANGES: update. <Florent Kermarrec>
    * | | | | | | bd8a4100 - cpu/minerva: add pythondata and use it to compile the sources. <Florent Kermarrec>
    * | | | | | | e4a4659d - litex_setup: add nmigen dependency (used to generate Minerva CPU). <Florent Kermarrec>
    * | | | | | | d3e3ca06 - CHANGES: start listing changes for next release. <Florent Kermarrec>
    |/ / / / / /
    * | / / / / 3c70c83f - cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs. <Florent Kermarrec>
    | |/ / / /
    |/| | | |
    * | | | | bb70a232 - cpu/software: move CPU specific software from the BIOS to the CPU directories. <Florent Kermarrec>
    * | | | | 0abc7d4f - cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository. <Florent Kermarrec>
    * | | | | b82b3b7e - integration/soc: rename usb_cdc to usb_acm. <Florent Kermarrec>
    * | | | | 0a1afbf6 - litex/__init__.py: remove retro-compat > 6 months old. <Florent Kermarrec>
    * | | | | 3531a641 - soc: allow passing custom CPU class to SoC. <Florent Kermarrec>
    | | | * | 83f4dcb2 - Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv <Ilya Epifanov>
    | | |/ /
    | |/| |
    | | | * 64b50515 - Add RDIMM side-B inversion support <David Shah>
    | |_|/
    |/| |
    * | |   90a6343d - Merge pull request #488 from enjoy-digital/python3.5 <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 9941e4c1 - travis: add back test on python3.5 (python3.6 is recommended but we can try to keep 3.5 compatibility until we have good reason to no longer support it). <Florent Kermarrec>
    |/ /
    * |   855d614e - Merge pull request #481 from betrusted-io/unfstringify <enjoy-digital>
    |\ \
    | * | 17b76654 - propose patch to not break litex for python 3.5 <bunnie>
    |/ /
    * | 56aa7897 - create first release, add CHANGES and note about Python modules in README. <Florent Kermarrec>
    * | 6d0896de - cpu/serv: switch to pythondata package instead of local git clone. <Florent Kermarrec>
    * | 1b069268 - README: update Python minimal version to 3.6. <Florent Kermarrec>
    * | ff61b1f6 - litex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX data. <Florent Kermarrec>
    * |   4d86ab9d - Merge pull request #399 from mithro/litex-sm2py <enjoy-digital>
    |\ \
    | * \   317ea7ed - Merge branch 'master' into litex-sm2py <enjoy-digital>
    | |\ \
    | * | | 1f356695 - litex_sim: Find tapcfg from pythondata module. <Tim 'mithro' Ansell>
    | * | | 3aee8a52 - Remove directories from submodules from MANIFEST.in file. <Tim 'mithro' Ansell>
    | * | | ebcb2a44 - Rename litex-data-XXX-YYY to pythondata-XXX-YYY <Tim 'mithro' Ansell>
    | * | | a39a4ec2 - Only allow fast-forward pulls. <Tim 'mithro' Ansell>
    | * | | e618d41f - Fixing mor1kx data finding. <Tim 'mithro' Ansell>
    | * | | 2e3b7f20 - Fix typo in error message. <Tim 'mithro' Ansell>
    | * | | 83b25813 - Fix the libcompiler_rt path. <Tim 'mithro' Ansell>
    | * | | 1c1c5bcb - Remove submodules. <Tim 'mithro' Ansell>
    | * | | c96d1e66 - Fix import for data. <Tim 'mithro' Ansell>
    | * | | 119985f3 - Use the current directory you are running. <Tim 'mithro' Ansell>
    | * | | 69367f8d - Make litex a namespace. <Tim 'mithro' Ansell>
    | * | | 3ae4f8f2 - Adding missing vexriscv CPU. <Tim 'mithro' Ansell>
    | * | | ac3fd794 - Adding missing comma. <Tim 'mithro' Ansell>
    | * | | 3df6c0c8 - Adding litex-data-software-compiler_rt as a required package. <Tim 'mithro' Ansell>
    | * | | 3964565e - Fixed quotes in `litex_setup.py` <Tim 'mithro' Ansell>
    | * | | d5a21a75 - Converting litex to use Python modules. <Tim 'mithro' Ansell>
    |  / /
    * | | 5ef869b9 - soc/cpu: add memory_buses to cpus and use them in add_sdram. <Florent Kermarrec>
    * | | 467fee3e - soc/cpu: rename cpu.buses to cpu.periph_buses. <Florent Kermarrec>
    |/ /
    * |   05815c4e - Merge pull request #477 from shuffle2/patch-1 <enjoy-digital>
    |\ \
    | * | f71014b9 - diamond: fix include paths <shuffle2>
    |/ /
    * | 4dece4ce - soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). <Florent Kermarrec>
    * |   c5ef9c73 - Merge pull request #473 from fjullien/memusage <enjoy-digital>
    |\ \
    | * | 3892d7a9 - bios: print memory usage <Franck Jullien>
    * | | 9460e048 - tools/litex_sim: use similar analyzer configuration than wiki. <Florent Kermarrec>
    * | |   443cc72d - Merge pull request #476 from enjoy-digital/serv <enjoy-digital>
    |\ \ \
    | * | | 1d1a4ecd - software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning. <Florent Kermarrec>
    | * | | fb9e369a - serv: connect reset. <Florent Kermarrec>
    | * | | 71778ad2 - serv: update copyrights (Greg Davill found the typos/issues). <Florent Kermarrec>
    | * | | 1f9db583 - serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :). <Florent Kermarrec>
    | * | | 2efd939d - serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill). <Florent Kermarrec>
    | * | | 22c39236 - initial SERV integration. <Florent Kermarrec>
    | | |/
    | |/|
    * | | c4c891de - build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis). <Florent Kermarrec>
    * | |   192849f0 - Merge pull request #475 from gregdavill/read_verilog_defer <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | 642c4b30 - build/trellis: add verilog_read -defer option to yosys script <Greg Davill>
    |/ /
    * | 96e7e6e8 - bios/sdram: reduce number of scan loops during cdly scan to speed it up. <Florent Kermarrec>
    * | 43e1a5d6 - targets/kcu105: use cmd_latency=1. <Florent Kermarrec>
    * | 85a059bf - bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal. <Florent Kermarrec>
    * | 038e1bc0 - targets/kc705: manual DDRPHY_CMD_DELAY no longer needed. <Florent Kermarrec>
    * | aaed4b94 - bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle. <Florent Kermarrec>
    * |   33c7b2ce - Merge pull request #472 from antmicro/jboc/sdram-calibration <enjoy-digital>
    |\ \
    | * | ab92e81e - bios/sdram: add automatic cdly calibration during write leveling <Jędrzej Boczar>
    * | |   4608bd18 - Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | b0f8ee98 - litex_sim: add option to create SDRAM module from SPD data <Jędrzej Boczar>
    * | | 0b3c4b50 - soc/cores/spi: add optional aligned mode. <Florent Kermarrec>
    * | | 6bb22dfe - cores/spi: simplify. <Florent Kermarrec>
    * | | fc434af9 - build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt). <Florent Kermarrec>
    * | | 1457c320 - xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale. <Florent Kermarrec>
    * | | 69462e66 - build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input. <Florent Kermarrec>
    * | | 65e6ddc6 - lattice/common: add LatticeECP5DDRInput. <Florent Kermarrec>
    * | | 2031f280 - lattice/common: cleanup instances, simplify tritates. <Florent Kermarrec>
    * | | 2d25bcb0 - lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput. <Florent Kermarrec>
    | |/
    |/|
    * | 56e15284 - platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. <Florent Kermarrec>
    * | 08e4dc02 - tools/remote/etherbone: update import. <Florent Kermarrec>
    |/
    * 19f983c4 - targets: manual define of the SDRAM PHY no longer needed. <Florent Kermarrec>
    * c0f3710d - bios/sdram: update/simplify with new exported LiteDRAM parameters. <Florent Kermarrec>
    * 3915ed97 - litex_sim: add phytype to PhySettings. <Florent Kermarrec>
    * c0c5ae55 - build/generic_programmer: move requests import to do it only when needed. <Florent Kermarrec>
    * c9ab5939 - bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4. <Florent Kermarrec>

 * litex-boards changed from cb95962 to 0b11aba
    * 0b11aba - platforms/nexys_video: add spisdcard pins. <Florent Kermarrec>
    * 76df4e3 - targets: simplify Ethernet/Etherbone integration on targets with both. <Florent Kermarrec>
    * 2e1a816 - pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone. <Florent Kermarrec>
    *   33fe308 - Merge pull request #78 from antmicro/jboc/spd-read <enjoy-digital>
    |\
    | * e5578a1 - zcu104/platform: change I2C number to 0 <Jędrzej Boczar>
    | * ac1f1cd - zcu104: add I2C <Jędrzej Boczar>
    * | 71f220a - colorlight_5a_75b: remove unnecessary parenthesis. <Florent Kermarrec>
    * | 2f3817c - pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst. <Florent Kermarrec>
    * | f19bc36 - pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer. <Florent Kermarrec>
    * | d6518c7 - prog/openocd: fix openocd_xc6 cfgs. <Florent Kermarrec>
    * | 22f18f6 - pano_logic_g2: move gmii_rst_n to _CRG. <Florent Kermarrec>
    * |   935a711 - Merge pull request #77 from skiphansen/master <enjoy-digital>
    |\ \
    | * | 0648c04 - Updated comment, added link to clocking documentation. <Skip Hansen>
    | * | 1ab4656 - Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200) <Skip Hansen>
    |/ /
    * | 9b572ec - forest_kitten_33: add minimal target and use es1. <Florent Kermarrec>
    * |   7ad0363 - Merge pull request #76 from gsomlo/gls-nexys4-spisdcard <Tim Ansell>
    |\ \
    | * | 435913f - platforms/nexys4ddr: add option to build with spi-mode sdcard support <Gabriel Somlo>
    |/ /
    * | 0d549a8 - platforms: add forest_kitten_33 initial platform suppport. <Florent Kermarrec>
    * | 12b54a7 - platforms/alveo_u250: add clk300 clock constraints. <Florent Kermarrec>
    * | 46f78b5 - nexys_video: add usb_fifo pins. <Florent Kermarrec>
    * | 445338e - platforms/nexys_video: add specific openocd cfg (use channel 1). <Florent Kermarrec>
    * | 5aeb7d8 - targets/acorn_cle_215: fix typo in description. <Florent Kermarrec>
    * | eeba64d - targets: use soc.build_name in load/flash bitstream. <Florent Kermarrec>
    * | 76551de - platforms/nexys_video: add sdcard pins, move clk/rst to top. <Florent Kermarrec>
    * | 83457b8 - platforms/arty: add _sdcard_pmod_io. <Florent Kermarrec>
    * | 8158d94 - targets/c10lprefkit: switch to litehyperbus. <Florent Kermarrec>
    * | 587caf7 - paltforms/marblemini: add break_off_pmod. <Florent Kermarrec>
    * | c2cd863 - platforms/ecp5_evn: rename spiflash1x to spiflash, rewrite hardware/configuration description and remove make_spiflash. <Florent Kermarrec>
    * |   3f0f120 - Merge pull request #70 from ilya-epifanov/ecp5-evn-spi1x-and-flash-params <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 0ba8045 - Added spiflash1x pins, a method to create an SpiFlash instance and a note on a second UART channel of FT2232H <Ilya Epifanov>
    * | b9ee3a7 - alveo_u250: re-organize the auto-generated IOs, add build/load parameters. <Florent Kermarrec>
    * | c0b7afc - targets/alveo_u250: +x. <Florent Kermarrec>
    * | 67d2a49 - tools/extract_xdc_pins: +x. <Florent Kermarrec>
    * | 482d7a6 - targets/pcie: use 128-bit datapath and 8 max_pending_requests on pcie_x4 configurations. <Florent Kermarrec>
    * | 2bb7fce - targets/acorn_cle_215: add minimal instructions to reproduce the results. <Florent Kermarrec>
    * |   6757c4e - Merge pull request #71 from daveshah1/alveo_u250 <enjoy-digital>
    |\ \
    | * | 088ccec - Add Alveo U250 platform and target <David Shah>
    | |/
    * | c7404e3 - targets/acorn_cle_215: switch to MT41K512M16 (Acorn has a 1GB DDR3 vs 512MB on NiteFury). <Florent Kermarrec>
    * | d05b10f - target/camlink_4k: add missing import. <Florent Kermarrec>
    * | b211c43 - test/test_targets: add acorn_cle_215 and marblemini. <Florent Kermarrec>
    * | 4faa91c - platforms/marblemini: review/cleanup. <Florent Kermarrec>
    * |   4ffdcb5 - Merge pull request #75 from jersey99/marblemini <enjoy-digital>
    |\ \
    | * | e4ccfcf - platforms/marblemini.py: Cleanup. Add openocd for programming marblemini <Vamsi K Vytla>
    | * |   a7d6de7 - Merge branch 'master' into marblemini <Vamsi K Vytla>
    | |\ \
    | * | | 5f7f087 - community/platforms/marblemini.py: Added marblemini from https://github.com/berkeleylab/marble-mini/ <Vamsi K Vytla>
    |  / /
    * | | 6f22f08 - targets: add LedChaser on platforms with user_leds. <Florent Kermarrec>
    * | |   b9a0f23 - Merge pull request #74 from tommythorn/master <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 6335717 - targets/orangecrab.py: propagate command arguments <Tommy Thorn>
    * | | 19b12fd - targets/panol_logic_g2: replace with a minimal target. <Florent Kermarrec>
    * | | 99c0435 - platforms/pano_logic_g2: simplify/cleanup. <Florent Kermarrec>
    * | | 6b5492a - pano_logic_g2: add copyrights. <Florent Kermarrec>
    * | | 6ddd859 - add pano_logic_g2 from litex-buildenv. <Florent Kermarrec>
    * | | 27c242b - targets/pcie: switch to PCIe X4 on all boards that support it. <Florent Kermarrec>
    * | | f993953 - targets/pcie: update LitePCIe constraints. <Florent Kermarrec>
    |/ /
    * | d34c3ba - prog: use different openocd config files for FT232/FT2232. <Florent Kermarrec>
    * | 117d1a1 - prog: add colorlight_5a_75b openocd config. <Florent Kermarrec>
    * | e500d90 - platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode. <Florent Kermarrec>
    * | 59e8c2c - acorn_cle_215: add .bin generation and --flash argument, working on hardware :). <Florent Kermarrec>
    * | a049fa6 - add Acorn CLE 215+ platform/target. <Florent Kermarrec>
    * | da61aab - targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets. <Florent Kermarrec>
    * | b58b9b9 - platforms: fix CI. <Florent Kermarrec>
    * | 2d9543b - targets: add build/load parameters on all targets. <Florent Kermarrec>
    * | 19eb570 - platforms: make sure all traditional platforms have a create_programmer method. <Florent Kermarrec>
    * | 84468c2 - targets/CRG: platforms are now automatically constraining the input clocks. <Florent Kermarrec>
    * | 1f88a9d - platforms: make sure clocks inputs are constraints on all platforms. <Florent Kermarrec>
    * | 86648ec - platforms/vcu118: rename ddram_second_channel to ddram:1. <Florent Kermarrec>
    * | e1820c7 - platforms/ac701: indent HPC. <Florent Kermarrec>
    * | 2129b67 - platforms: make sure all plarforms have separators. <Florent Kermarrec>
    * | ea0eda9 - platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series. <Florent Kermarrec>
    * | 588bbac - add prog directory with some Xilinx OpenOCD configurations files. <Florent Kermarrec>
    * | 78b5727 - targets: rename usb_cdc to usb_acm. <Florent Kermarrec>
    |/
    * 2213d73 - targets/kcu105: use cmd_latency=1. <Florent Kermarrec>
    * a8a42c5 - targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed. <Florent Kermarrec>
    * 865b01e - ecpix5: add ethernet. <Florent Kermarrec>
    * 6fe4c4e - ecpix5: add DDR3 (working) <Florent Kermarrec>
    * efb13bc - add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working. <Florent Kermarrec>
    * 4154bdf - targets/PCIe: add PCIe software reset. <Florent Kermarrec>
    * 4ad6042 - platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. <Florent Kermarrec>
    * 4185a01 - targets: manual define of the SDRAM PHY is no longer needed. <Florent Kermarrec>

 * migen changed from 0.6.dev-337-g19d5eae to 0.6.dev-347-gb1b2b29
    * b1b2b29 - zc706: redo FMC connectors <Astro>
    * 0d16e03 - kasli: add DCXO pins <Sebastien Bourdeauducq>
    * ea1eefe - zc706: add FMC HPC connector HA pins <Astro>
    * dc9cfe6 - kasli2: add upper EEMs <Sebastien Bourdeauducq>
    * 6809ee0 - kasli2: add cdr_clk and cdr_clk_clean <Sebastien Bourdeauducq>
    * afc6b02 - zc706: fix LAxx_CC pin naming consistency with KC705 <Sebastien Bourdeauducq>
    * 0762612 - zc706: add user_sma_clock <Sebastien Bourdeauducq>
    * e71f21e - zc706: add FMC connectors <Astro>
    * 5b5e4fd - kasli: typo <Sebastien Bourdeauducq>
    * bea0bdc - kasli: v2.0 support (WIP) <Sebastien Bourdeauducq>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 d62fd24c81c54dae6eb7f06092316215b73237ad litedram (2020.04-43-gd62fd24)
 0feed1720d0063ff67210728ecfe422891f809e0 liteeth (2020.04-7-g0feed17)
 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04)
 b0e8383d6179ee81a708204d4db9263d6fadc6c8 litepcie (2020.04-12-gb0e8383)
 2e5c5b12d52f695f4560ca7dd08b4170d7568715 litesata (2020.04)
 54488c0f4d6e9e953f1a0de3d578915a5e4ccddf litescope (2020.04)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
 77139289f86a412deb0da7f783ea44ded5e05900 litex (2020.04-260-g77139289)
 0b11aba8a18a9e38f6a49e7f291c072e80e3224e litex-boards (2020.04-71-g0b11aba)
 7da392963878842f93f09a7a218c1052ae5e45d6 litex-renode (remotes/origin/HEAD)
 b1b2b298b85a795239daad84c75be073ddc4f8bd migen (0.6.dev-347-gb1b2b29)
 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this issue Jun 25, 2020
@mateusz-holenko
Updating submodules.
237f16a 
 * litedram changed from de55a8e to d62fd24
    *   d62fd24 - Merge pull request #201 from antmicro/jboc/spd-read <enjoy-digital>
    |\
    | * 4233f86 - modules/spd: save SPD data in SDRAMModule to allow for runtime verification <Jędrzej Boczar>
    * | f23cb80 - litedram_gen: revert builder.build(..., regular_comb=False). <Florent Kermarrec>
    * | d1db115 - litedram_gen: review/simplify #197. <Florent Kermarrec>
    * |   a8e281f - Merge pull request #197 from ozbenh/standalone-sim <enjoy-digital>
    |\ \
    | * | d0f0c94 - phy/model: Don't generate empty mem_*.init files <Benjamin Herrenschmidt>
    | * | b8d6da5 - gen: Allow generation of a standalone sim model <Benjamin Herrenschmidt>
    * | |   83b9a1d - Merge pull request #199 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \ \
    | |/ /
    |/| /
    | |/
    | * cbe91bc - modules: add function for parsing SPD EEPROM dumps from BIOS firmware <Jędrzej Boczar>
    * | 639a31f - test/test_timing: update test_txxd_controller. <Florent Kermarrec>
    * | 3c1ab76 - litedram/common/tXXDController: only set reset to 1 when txxd is None. <Florent Kermarrec>
    |/
    *   e95af3f - Merge pull request #195 from enjoy-digital/bios-libs <enjoy-digital>
    |\
    | * fe48a92 - test/reference: update. <Florent Kermarrec>
    | * c30910a - init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS. <Florent Kermarrec>
    |/
    * 5078b19 - core/crossbar: remove retro-compat > 6 months old. <Florent Kermarrec>
    * 3b105d5 - modules: fix SDRAMRegisteredModule. <Florent Kermarrec>
    *   b2a5685 - Merge pull request #189 from daveshah1/ddr4_rdimm_init <enjoy-digital>
    |\
    | * 70054ba - Add support for DDR4 RDIMMs <David Shah>
    * | 7ae4ad5 - modules: add SDR/DDR/DDR2/DDR3/DDR4 SDRAMModule (and Registered versions). <Florent Kermarrec>
    * | 1f7d9eb - litedram_gen: pass FPGA speedgrade to iodelay_pll. <Florent Kermarrec>
    * | f4871b9 - litedram_gen: use default settings on wb_bus. <Florent Kermarrec>
    * | 6fb8396 - litedram_gen: remove csr_base (no longer needed since CPUNone type will automatically set csr mapping to 0x00000000) and create a use bus with the same address_width as the main bus of the SoC. <Florent Kermarrec>
    * | 94c215e - litedram_gen: review/simplify #193, always add ddrctrl. <Florent Kermarrec>
    * |   f036ec2 - Merge pull request #193 from ozbenh/standalone-cores <enjoy-digital>
    |\ \
    | * | 04717b4 - gen: Rename standalone core wishbone <Benjamin Herrenschmidt>
    | * | b0838f7 - gen: Add option to specify CSR alignment <Benjamin Herrenschmidt>
    | * | d5a03b3 - gen: Add option to generate DDRCTL on standalone cores <Benjamin Herrenschmidt>
    | * | efad6b3 - gen: Add option to specify CSR base for standalone cores <Benjamin Herrenschmidt>
    | * | c91cbb5 - gen: Remove obsolete bus_expose config option <Benjamin Herrenschmidt>
    |/ /
    * | 4e539ad - litedram_gen: switch to SoCCore. <Florent Kermarrec>
    * | ac33d29 - litedram_gen: simplify and expose bus when CPU is set to None. <Florent Kermarrec>
    * | fe47838 - litedram_gen: expose a Bus Slave port instead of a CSR port. <Florent Kermarrec>
    * | 52b49fb - test/reference: update. <Florent Kermarrec>
    * | 52ca393 - modules: add MT41J512M16/MT41K512M16. <Florent Kermarrec>
    * | 589957f - phy: extend Bitslip capability to 2 sys_clk cycles. <Florent Kermarrec>
    * | 5c0231d - common/BitSlip: add cycles parameter to extend bitstlip to multiple system clock cycles. <Florent Kermarrec>
    * | ed0810a - gen: Optionally pass cpu_variant from YAML to SoC <Benjamin Herrenschmidt>
    |/
    *   dfe6f90 - Merge pull request #188 from daveshah1/ddr4_dimm_x4 <enjoy-digital>
    |\
    | * 5b4381b - usddrphy: Support for x4 chip based DIMMs <David Shah>
    * |   9f136c0 - Merge pull request #187 from daveshah1/add_MTA18ASF2G72PZ <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 97f0a37 - modules: Add MTA18ASF2G72PZ DDR4 RDIMM <David Shah>
    |/
    * 9a2d3f0 - common: add PHYPadsReducer to only use specific DRAM modules. <Florent Kermarrec>
    * 20a849c - test/reference: update ddr4_init.h <Florent Kermarrec>
    *   cec3a99 - Merge pull request #181 from antmicro/jboc/eeprom-timings <enjoy-digital>
    |\
    | * 312bce2 - modules: pass rate automatically when creating module from SPD data <Jędrzej Boczar>
    | * 07bbd79 - modules: update existsing SO-DIMM timings based on SPD data <Jędrzej Boczar>
    | * cf83ac6 - test: improve SPD tests of Micron DDR3 SO-DIMM modules <Jędrzej Boczar>
    | * 854a614 - modules: fix calculations of speedgrade from tck in SPD data <Jędrzej Boczar>
    | * c744204 - modules: fix nrows in MT8KTF51264 <Jędrzej Boczar>
    | * 3980e06 - modules: add option to load module parameters from SPD data <Jędrzej Boczar>
    * | 48c2fc2 - phy: simplify/improve dqs preamble/postamble. <Florent Kermarrec>
    * | eaf0691 - phy/ecp5ddrphy: simplify, working with dqs preamble/postamble. <Florent Kermarrec>
    * | 12a017f - phy/ecp5ddrphy: simplify/cleanup. <Florent Kermarrec>
    * | 62915cd - phy: rework BitSlip to simplify integration, add DQSPattern module. <Florent Kermarrec>
    * | 9ff9e82 - phy/usddrphy: move pads.ten control to control block. <Florent Kermarrec>
    * | 91a9a2a - phy/ecp5ddrphy: fix dqs preamble/postamble control. (make it similar to 7-series/Ultrascale). <Florent Kermarrec>
    * | 5d29686 - phy/s7ddrphy/usddrphy: more compact write dqs postamble/preamble control path. <Florent Kermarrec>
    * | 8d0e7f6 - phy/usddrphy: simplify/cleanup write control path/dqs postamble/preamble control path. <Florent Kermarrec>
    * | 57b16c2 - phy/usddrphy: simplify/cleanup write control path, add DQS Pre/Postamble support. <Florent Kermarrec>
    * | 1462a43 - phy/usddrphy: cleanup/simplify read control path. <Florent Kermarrec>
    * | cd671f9 - phy/s7ddrphy: cleanup/simplify read control path. <Florent Kermarrec>
    * | d061e60 - test/reference: update. <Florent Kermarrec>
    * | 45a03df - phy/init: add phytype to PhySettings and export more parameters to C header to simplify software. <Florent Kermarrec>
    * | 2df9004 - init: improve ident. <Florent Kermarrec>
    * | eca7fc2 - phy/ecp5ddrphy: remove Bitslip from comment (no longer present). <Florent Kermarrec>
    * | f4f2948 - phy/ecpddrphy: remove Bitslip (not used and redundant with dqs_read) and use BitSlip software control to move dqs_read. <Florent Kermarrec>
    * | e2b4c2b - phy/ecp5ddrphy: cosmetics. <Florent Kermarrec>
    |/
    * f68f1dd - phy/ecp5ddrphy/control: cleanup/simplify and document (no functional changes). <Florent Kermarrec>
    * fdf7c76 - phy/control: cleanup/simplify (no functional changes). <Florent Kermarrec>
    * a767618 - phy: improve flow control readability (add separators between Read/Write/Write DQS Postamble/Preamble parts). <Florent Kermarrec>

 * liteeth changed from 705003e to 0feed17
    * 0feed17 - phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work). <Florent Kermarrec>
    * 53c9eb9 - core/ip: move mcase_oui/ip_mask definition to common and set target_mac with NextValue. <Florent Kermarrec>
    *   58e1681 - Merge pull request #41 from shuffle2/mcast <enjoy-digital>
    |\
    | * 6d00ec1 - iptx: support multicast mac and bypass arp table <Shawn Hoffman>
    * | 8afdec9 - phy/ecp5rgmii: review/simplify inband_status integration. <Florent Kermarrec>
    * |   55af430 - Merge pull request #40 from shuffle2/master <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 26c4e41 - ecp5rgmii: enable reading inband PHY_status <Shawn Hoffman>
    |/
    * dc67e6d - phy/ecp5rgmii: use DDROutput/DDRInput now available for ECP5. <Florent Kermarrec>

 * litepcie changed from 586ef78 to b0e8383
    * b0e8383 - frontend/dma/LitePCIeDMAReader: immediately return to IDLE state when disabled. <Florent Kermarrec>
    *   4e333cb - Merge pull request #29 from sergachev/master <enjoy-digital>
    |\
    | * 8192494 - kernel: remove unnecessary call to pci_release_regions() on device remove <Ilia Sergachev>
    |/
    * c2fd143 - phy/s7pciephy: expose disable_constraints parameter to use_external_hard_ip. <Florent Kermarrec>
    * 6049a69 - litepcie_gen: add optional Sphinx/Html doc generation with --doc. <Florent Kermarrec>
    * 6bb89af - phy/s7pciehy: disable constraints generated from the .xci and use our owns. <Florent Kermarrec>
    *   ef7d40e - Merge pull request #28 from sergachev/master <enjoy-digital>
    |\
    | * 3eb2b86 - test_dma: remove unused imports and variables, fix mistypes <Ilia Sergachev>
    |/
    *   9a3ada5 - Merge pull request #27 from sergachev/master <enjoy-digital>
    |\
    | * e637090 - dma: fix another couple of mistypes <Ilia Sergachev>
    | * 4c4e3bf - dma: fix mistypes in comments <Ilia Sergachev>
    |/
    * 3ca6e38 - frontend/dma/monitor: reduce count_width from 32-bit (default) to 16-bit. <Florent Kermarrec>
    * 22faa07 - litepcie_gen: add pcie_data_width support. <Florent Kermarrec>
    *   96a6cdc - Merge pull request #25 from sergachev/master <enjoy-digital>
    |\
    | * 5804b43 - software: fix definitions <Ilia Sergachev>
    * 0496daf - litepcie_gen: add buffers on DMA sink/source to ensure data are clocked on LitePCIe interface and ease integration. <Florent Kermarrec>
    * 7818ace - frontend/dma: fix level CSRStatus size (+1). <Florent Kermarrec>
    * a85b1d7 - tlp/controller: expose cmp_bufs_buffered parameter. <Florent Kermarrec>
    * 264d7f3 - frontend/dma: allow asymetric writer/reader buffering depths. <Florent Kermarrec>
    * 9cb938e - frontend/dma: expose table_depth parameter. <Florent Kermarrec>
    * a6d836e - gen/examples: add software reset. <Florent Kermarrec>

 * litex changed from 2d018826 to 77139289
    *   77139289 - Merge pull request #552 from ozbenh/memspeed-long <Tim Ansell>
    |\
    | * 6239eac1 - sdram: Use unsigned long for memory test <Benjamin Herrenschmidt>
    * |   a116578c - Merge pull request #550 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \
    | * | a433c837 - bios/litedram: add option to verify SPD EEPROM memory contents <Jędrzej Boczar>
    | * | 1692dfbf - build/sim/spdeeprom: use hex format when loading from file <Jędrzej Boczar>
    * | |   b98a9192 - Merge pull request #549 from antmicro/mglb/fix-vivado-yosys <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | a4e83234 - build/xilinx: do not assume build name is "top" <Mariusz Glebocki>
    |/ /
    * |   5cc7a988 - Merge pull request #547 from gsomlo/gls-fix-sdcard-status <enjoy-digital>
    |\ \
    | * | 28290efd - soc/software/litesdcard: update for response register back to 128 bits <Gabriel Somlo>
    * | | 395af900 - interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify. <Florent Kermarrec>
    * | | 511832a9 - soc/interconnect/axi: generate wishbone.sel for reads. <Florent Kermarrec>
    * | | 4f82a36a - soc/software: only keep 32-bit CSR alignment support. <Florent Kermarrec>
    |/ /
    * | 75936775 - wishbone/wishbone2csr: use wishbone.sel on CSR write. <Florent Kermarrec>
    * | b1ec092e - soc/software/litesdcard: use new send register to send command and remove CSR8_CMD_FIX. <Florent Kermarrec>
    * | efcba14b - platforms/nexys_video: add spisdcard pins. <Florent Kermarrec>
    * | 119ce56f - targets/nexys_video: add spi-sdcard and sdcard support. <Florent Kermarrec>
    * | cc595017 - plaforms/nexys_video: keep up to date with litex-boards. <Florent Kermarrec>
    * | 5cc564fb - targets: simplify Ethernet/Etherbone integration on targets with both. <Florent Kermarrec>
    * | 55c7461e - bios/cmds/cmd_litesdcard: rewrite comments/descriptions. <Florent Kermarrec>
    * | 6cb03963 - bios/main: replace / with -. <Florent Kermarrec>
    * |   5dd5f97b - Merge pull request #545 from gsomlo/gls-fix-mmptr <enjoy-digital>
    |\ \
    | * | 3e1b17d4 - csr: fix simple accessor alignment <Gabriel Somlo>
    * | | 6c1e2d84 - software/liblitesdcard: replace hexdump with dump_bytes already available in the BIOS. <Florent Kermarrec>
    |/ /
    * | 9e068a74 - soc/add_sdcard: add with_emulator parameter to use SDCard emulator (from Google Project Vault) and integrate it in litex_sim. <Florent Kermarrec>
    * | 2ae55e80 - setup.py: add litex_jtag_uart and litex_crossover_uart to console_scripts. <Florent Kermarrec>
    * | 62d939e8 - Merge pull request #543 from antmicro/jboc/eeprom-sim <enjoy-digital>
    |\|
    | * a0ce4ce5 - litex/build/sim: add module for simulating SPD EEPROM <Jędrzej Boczar>
    * | c4f96318 - targets/nexys4ddr: fix sdcard assert. <Florent Kermarrec>
    * | 76cc112e - bios: add main bus and csr bus infos, use KiB/GiB. <Florent Kermarrec>
    |/
    * 02072dea - integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically. <Florent Kermarrec>
    * 4b3afa75 - integration/soc: add add_sdcard method with integration code from nexys4ddr. <Florent Kermarrec>
    * c78caeb9 - csr: Fix definition(s) of CSR_BASE in generated headers <Benjamin Herrenschmidt>
    * f8bb500a - liblitedram/sdram: Add option to disable cdelay() <Benjamin Herrenschmidt>
    * 6d72ef28 - cpu/serv: add variants. <Florent Kermarrec>
    * fd7ec50e - soc/integration/export: add optional csr_base parameter. <Florent Kermarrec>
    * 795ff08a - build/sim/verilator: add regular_comb parameter (that defaults to False) and pass it to get_verilog. <Florent Kermarrec>
    *   25d2e7c9 - Merge pull request #542 from gsomlo/gls-sdcard-followup <enjoy-digital>
    |\
    | * 6da98ca1 - software/bios: fixup sdclk command <Gabriel Somlo>
    * |   3fd6ecd8 - Merge pull request #541 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \
    | * | 1172c10a - bios: move I2C from liblitedram to libbase <Jędrzej Boczar>
    | * | 472bf9ac - bios/sdram: expose I2C functions <Jędrzej Boczar>
    | * | bdc7eb5c - litex_sim: load SPD data from files in hexdump format as printed in BIOS <Jędrzej Boczar>
    | * | a42dc974 - bios/sdram: add BIOS command for reading SPD <Jędrzej Boczar>
    | * | 8fd3e74e - bios/sdram: add firmware for reading SPD EEPROM <Jędrzej Boczar>
    * | | 68f83cbc - CHANGES: document deprecated/moved modules. <Florent Kermarrec>
    * | | ab806060 - soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone. <Florent Kermarrec>
    * | | 0a3d649a - interconnect/wishbone: integrate Wishbone2CSR. <Florent Kermarrec>
    * | | b5b88d27 - interconnect/csr_bus: add separators. <Florent Kermarrec>
    * | | 86952a6e - interconnect/wishbone: remove CSRBank (probably not used by anyone). <Florent Kermarrec>
    * | | e404608c - interconnect/wishbone: add separators and move SDRAM/Cache. <Florent Kermarrec>
    * | | 1fddd0e3 - interconnect/wishbone: simplify DownConverter. <Florent Kermarrec>
    * | | e0d26820 - interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten). <Florent Kermarrec>
    | |/
    |/|
    * | 696b31ed - tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM. <Florent Kermarrec>
    * | 2efcf879 - targets/nexys4ddr: update add_sdcard method. <Florent Kermarrec>
    * | 2934c085 - CHANGES: add JTAG UART. <Florent Kermarrec>
    * | 3b47d4a4 - tools/litex_jtag_uart: add openocd config and telnet port parameters. <Florent Kermarrec>
    * | 67cf6703 - cpus: remove common cpu variants/extensions definition and simplify variant check. <Florent Kermarrec>
    * | 062ff67e - cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin. <Florent Kermarrec>
    * | 24687cbd - tools/litex_client/RemoteClient: add base_address parameter. <Florent Kermarrec>
    * | 78a9579e - cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word. <Florent Kermarrec>
    * |   370e4652 - Merge pull request #539 from dayjaby/pr-fix_uart_startbit <enjoy-digital>
    |\ \
    | * | e853ad4b - fix uart startbit: 1 cycle later <David Jablonski>
    * | | c75cf45a - tools: add litex_jtag_uart to create a virtual uart for the jtag uart. <Florent Kermarrec>
    * | | 2cf83b9f - tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now. <Florent Kermarrec>
    * | | bed5aafd - tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...). <Florent Kermarrec>
    * | | 3833bc3e - litex_sim: override uart_name to sim only for serial. <Florent Kermarrec>
    * | | da7fd308 - CHANGES: update. <Florent Kermarrec>
    * | | 2fb52e66 - integration/soc: remove TODO in header. <Florent Kermarrec>
    * | | b65f18c3 - cpu/cv32e40p: fix copyright year. <Florent Kermarrec>
    * | | 30f35170 - cpu/cv32e40p: add copyright and improve indentation. <Florent Kermarrec>
    * | | b23702ec - litex_setup/pythondata-cpu-cv32e40p: clone in recursive mode. <Florent Kermarrec>
    * | |   4c4cd335 - Merge pull request #535 from antmicro/arty-cv32e40p <enjoy-digital>
    |\ \ \
    | * | | 2d6ee5aa - cores/cpu: add cv32e40p <Piotr Binkowski>
    | * | | ca8cb834 - software/bios/isr: add support for cv32e40p <Piotr Binkowski>
    | * | | 2903b1bf - litex_setup: add pythondata for cv32e40p <Piotr Binkowski>
    * | | |   7d09ea19 - Merge pull request #538 from antmicro/fix_libbase <enjoy-digital>
    |\ \ \ \
    | * | | | 9d16b0fc - libbase: Include missing uart header <Mateusz Hołenko>
    |/ / / /
    * | | | 3d06dc02 - test/test_targets: update build_test. <Florent Kermarrec>
    * | | | 42350f6d - platforms/targets: keep in sync with litex-boards. <Florent Kermarrec>
    * | | | 2eea7864 - build/sim: rename dut to sim (for consistency with other builds). <Florent Kermarrec>
    * | | | a6cbbc9d - integration/soc: set build_name to platform.name when not specified. <Florent Kermarrec>
    * | | | 16417cb8 - software/liblitespi: fix #endif location. <Florent Kermarrec>
    * | | |   9bdb063b - Merge pull request #516 from antmicro/i2s_support_arty <enjoy-digital>
    |\ \ \ \
    | * | | | ce499900 - Extend I2S capabilities <Pawel Sagan>
    * | | | |   c2e9a26e - Merge pull request #534 from fjullien/fix_litex_sim_warn <enjoy-digital>
    |\ \ \ \ \
    | |/ / / /
    |/| | | |
    | * | | | 7c5f56c2 - litex/sim: fix compiler warnings <Franck Jullien>
    |/ / / /
    * | | |   6fedaa70 - Merge pull request #533 from antmicro/fix-dummy-bits-function-name <enjoy-digital>
    |\ \ \ \
    | * | | | ab41e27e - software/liblitespi/spiflash: fix dummy bits setup function name <Jan Kowalewski>
    |/ / / /
    * | | | d71152ef - litex_setup: move requests import to avoid having to install it on travis. <Florent Kermarrec>
    * | | | 9854fdd5 - .travis: install  requests package before running litex_setup.py. <Florent Kermarrec>
    * | | | bd0f21ba - targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets). <Florent Kermarrec>
    * | | | 80eca300 - software/liblitespi/spiflash: review/simplify/update and test on arty. <Florent Kermarrec>
    * | | | 4a175620 - build/xilinx: simplify LITEX_ENV_ISE/VIVADO handling. <Florent Kermarrec>
    * | | | e91c3171 - software/bios: cleanup includes and specify the lib in the include. <Florent Kermarrec>
    * | | | c3a03d0d - software: create liblitespi and mode litespi code to it (with some parts commented out for now). <Florent Kermarrec>
    * | | | 61238bee - soc/software/bios: add autoconfiguration functionality for LiteSPI core <Jan Kowalewski>
    * | | | d3890055 - litex_setup: add automatic update of litex_setup (because it also changes) and be sure we are on master branch before update. <Florent Kermarrec>
    * | | |   939f546a - Merge pull request #531 from gsomlo/gls-bios-linker <enjoy-digital>
    |\ \ \ \
    | |_|/ /
    |/| | |
    | * | | c5524dbf - software/bios: fix link order to avoid undefined symbol errors <Gabriel Somlo>
    |/ / /
    * | | b4267a79 - build/xilinx: source settings64.sh automatically just before build if LITEX_ENV_ISE/LITEX_ENV_VIVADO environment variables are set. <Florent Kermarrec>
    * | | de7e0ee9 - integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed. <Florent Kermarrec>
    * | | 6f8f0d23 - litex_setup: add litehyperbus and remove hyperbus core/test. <Florent Kermarrec>
    |/ /
    * | 109fd267 - integration/builder: simplify default output_dir to "build/platform". <Florent Kermarrec>
    * | 55c0ddab - litex_setup: add sha1 support on git clone/pull and fix microwatt to a specific sha1. <Florent Kermarrec>
    |/
    *   23d43a2c - Merge pull request #530 from enjoy-digital/bios-libs <enjoy-digital>
    |\
    | * 7192397a - software/libbase: remove linker-sdram (unused). <Florent Kermarrec>
    | * b4b84def - software/bios: mode spisdcard code to liblitesdcard. <Florent Kermarrec>
    | * 21e2a34c - software/bios: rename commands to cmds and update with libs' names. <Florent Kermarrec>
    | * 33f6ce74 - software/bios: move hw flags definitions to respective libs, remove hw/flags.h. <Florent Kermarrec>
    | * 403355a8 - software: create liblitescard and move sdcard init/test code to it. <Florent Kermarrec>
    | * 920d0ee5 - software: create liblitedram and move sdram init/test code to it. <Florent Kermarrec>
    | * c95084e5 - bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash. <Florent Kermarrec>
    | * 573a8815 - software/bios/commands: rename cmd_mdio to cmd_liteeth. <Florent Kermarrec>
    | * ff8d9e61 - software/bios: move mdio to libliteeth. <Florent Kermarrec>
    | * 70a67ce7 - software/bios: rename libnet to libliteeth and move all ethernet files to it. <Florent Kermarrec>
    | * 56b8723b - software/bios: rename cmd_mem_access to cmd_mem. <Florent Kermarrec>
    |/
    * a02077d5 - cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build. <Florent Kermarrec>
    * b5352f40 - cpu/microwatt: update microwatt_wraper.vhdl <Florent Kermarrec>
    * be25500e - uptime: rework and integrate it in Timer to ease software support. <Florent Kermarrec>
    * d6549ff8 - bios: add uptime command and rewrite cmd_bios comments. <Florent Kermarrec>
    * fc0e55be - soc: improve uptime comments. <Florent Kermarrec>
    *   840679ad - Merge pull request #526 from rprinz08/master <enjoy-digital>
    |\
    | * 3f649077 - Make booting from SD-Card to behave same as from SPI flash <rprinz08>
    * | 82364de5 - soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled. <Florent Kermarrec>
    |/
    * 3391398a - bios/sdram: always show bitslip on two digits to keep scan aligned. <Florent Kermarrec>
    *   4a5072a0 - Merge pull request #517 from ozbenh/csr-access-rework <enjoy-digital>
    |\
    | * 1e35b0e7 - csr: Rework accessors <Benjamin Herrenschmidt>
    |/
    * d4f44597 - CHANGES: update. <Florent Kermarrec>
    *   a51c7a7b - Merge pull request #518 from enjoy-digital/csr_base <enjoy-digital>
    |\
    | * 748ef1ad - export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses. <Florent Kermarrec>
    * |   177c1e53 - Merge pull request #523 from DurandA/patch-5 <enjoy-digital>
    |\ \
    | * | 9d9e7d54 - Update litex_term help <Arnaud Durand>
    |/ /
    * | 2e59dc32 - platforms/nexys4ddr: add card detect pin to sdcard. <Florent Kermarrec>
    * | 51742be2 - integration/soc: review/simplify interconnect and add logger.info. <Florent Kermarrec>
    * |   78413cc0 - Merge pull request #519 from ozbenh/point2point <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 1ed68691 - soc: Revive generation of a PointToPoint interconnect <Benjamin Herrenschmidt>
    |/
    * 9f941138 - test/test_targets: workaround to fix travis. <Florent Kermarrec>
    * 9d1443c1 - cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that. <Florent Kermarrec>
    * 5ea3bae0 - bios/boot: review/fix #503. <Florent Kermarrec>
    *   bf7857f5 - Merge pull request #503 from rprinz08/master <enjoy-digital>
    |\
    | * 1f55fcf4 - fixed bug in BIOS spi flash "fw" command <rprinz08>
    | * f062c0c4 - removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram <rprinz08>
    | * ea232fc5 - BIOS boot firmware from SPI with address offset <rprinz08>
    * |   b4e349eb - Merge pull request #513 from mubes/bios_linker <enjoy-digital>
    |\ \
    | * | d2d82dac - Bios linker edits to prevent inappropriate optimisation <Dave Marples>
    |/ /
    * | 3fb99b7d - cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite. <Florent Kermarrec>
    * |   2a5a7536 - Merge pull request #478 from antmicro/extended_spi_flash <enjoy-digital>
    |\ \
    | * | 00f973ea - spi_flash: extend non-bitbanged flash support <Jakub Cebulski>
    | * | a344e20b - spi_flash: fix building without bitbang <Jakub Cebulski>
    * | |   7d79da8e - Merge pull request #510 from mubes/colorlight_usb <enjoy-digital>
    |\ \ \
    | * | | 84997332 - Fix dumb missing line <Dave Marples>
    | * | |   33e202ed - Bring into line with master <Dave Marples>
    | |\ \ \
    | * | | | dc1d4520 - Addition of boot address parameter for trellis builds <Dave Marples>
    * | | | | 3a6dd95d - integration/soc: review/simplify changes for standalone cores. <Florent Kermarrec>
    * | | | |   0d5eb133 - Merge pull request #511 from ozbenh/standalone-cores <enjoy-digital>
    |\ \ \ \ \
    | * | | | | f628ff6b - WB2CSR: Use CSR address_width for the wishbone bus <Benjamin Herrenschmidt>
    | * | | | | 520c17e9 - soc_core: Add option to override CSR base <Benjamin Herrenschmidt>
    | * | | | | ecbd4028 - soc: Don't update CSR alignment when there is no CPU <Benjamin Herrenschmidt>
    | * | | | | f28f2471 - soc: Don't create a wishbone slave to LiteDRAM with no CPU <Benjamin Herrenschmidt>
    | * | | | | dcc881db - soc: Don't create a share intercon with only one master and one slave <Benjamin Herrenschmidt>
    | | |/ / /
    | |/| | |
    * | | | | 873d95e5 - interconnect/wishbonebridge: refresh/simplify. <Florent Kermarrec>
    * | | | |   c136113a - Merge pull request #506 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \ \ \
    | * | | | | aed1d514 - Update README.md and core.py for BlackParrot <sadullah>
    | * | | | | 5e4a4360 - Vivado Command Update for Systemverilog <sadullah>
    | |/ / / /
    * | | | |   d2c9d385 - Merge pull request #508 from antmicro/update_litesdcard <enjoy-digital>
    |\ \ \ \ \
    | |/ / / /
    |/| | | |
    | * | | | 0db35069 - Update Litex bios to handle updated litesdcard. <Kamil Rakoczy>
    |/ / / /
    * | | |   3ce90100 - Merge pull request #505 from DurandA/patch-3 <enjoy-digital>
    |\ \ \ \
    | * | | | 2c40967b - Enable 1x mode on SPI flash <Arnaud Durand>
    | | |_|/
    | |/| |
    * | | | e2176cef - soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters. <Florent Kermarrec>
    * | | | 1e610600 - build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends. <Florent Kermarrec>
    * | | |   ebcf67c1 - Merge pull request #502 from shuffle2/master <enjoy-digital>
    |\ \ \ \
    | * | | | eeee179d - diamond: close project when done <Shawn Hoffman>
    | * | | | 9b782bd7 - diamond: clock constraint improvements <Shawn Hoffman>
    | |/ / /
    * | | |   80f5327e - Merge pull request #490 from daveshah1/rdimm_bside_init <enjoy-digital>
    |\ \ \ \
    | * \ \ \   13db89eb - Merge branch 'master' into rdimm_bside_init <enjoy-digital>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | c9e36d7f - lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args. <Florent Kermarrec>
    * | | | | ea7fe383 - lattice/trellis: simplify seed support and add it to trellis_args. <Florent Kermarrec>
    * | | | |   5ee01c94 - Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed <enjoy-digital>
    |\ \ \ \ \
    | * | | | | ac1e9683 - Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs` <Ilya Epifanov>
    * | | | | |   5987ddb4 - Merge pull request #485 from ilya-epifanov/cpu-imac-config-for-vexriscv <enjoy-digital>
    |\ \ \ \ \ \
    | * \ \ \ \ \   c5f74a5a - Merge branch 'master' into cpu-imac-config-for-vexriscv <enjoy-digital>
    | |\ \ \ \ \ \
    | |/ / / / / /
    |/| | | | | |
    * | | | | | | 59d88a88 - integration/soc/add_adapter: rename is_master to direction. <Florent Kermarrec>
    * | | | | | |   57390666 - Merge pull request #504 from sergachev/master <enjoy-digital>
    |\ \ \ \ \ \ \
    | * | | | | | | e4fa4bbc - integration/soc: fix add_adapter for slaves <Ilia Sergachev>
    |/ / / / / / /
    * | | | / / / 2d70220b - bios: Fix warning on 64-bit <Benjamin Herrenschmidt>
    | |_|_|/ / /
    |/| | | | |
    * | | | | | fbbbdf03 - core/led: simplify LedChaser (to have the same user interface than GPIOOut). <Florent Kermarrec>
    * | | | | | 05869beb - cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :)) <Florent Kermarrec>
    * | | | | | 90c485fc - integration/soc: add clock_domain parameter to add_etherbone. <Florent Kermarrec>
    * | | | | | f1a50a21 - integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge). <Florent Kermarrec>
    | |_|_|/ /
    |/| | | |
    * | | | | 79ee135f - bios/sdram: fix lfsr typo. <Florent Kermarrec>
    * | | | |   162d3260 - Merge pull request #500 from mubes/fixups <enjoy-digital>
    |\ \ \ \ \
    | * \ \ \ \   2a37b97d - Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups <Dave Marples>
    | |\ \ \ \ \
    | * | | | | | 967e38bb - Small fixups to address compiler warnings etc. <Dave Marples>
    | | |_|_|_|/
    | |/| | | |
    * | | | | | d74f8fc9 - build/xilinx: add disable_constraints parameter to Platform.add_ip. <Florent Kermarrec>
    | |/ / / /
    |/| | | |
    * | | | | 84841e1d - bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt). <Florent Kermarrec>
    * | | | | 99c5b0fc - bios/sdram: Use an LFSR to speed up pseudo-random number generation <Benjamin Herrenschmidt>
    * | | | |   34f26868 - Merge pull request #499 from DurandA/patch-2 <enjoy-digital>
    |\ \ \ \ \
    | * | | | | 5e049d89 - Add data dirs to manifest <Arnaud Durand>
    * | | | | | 8b9aa16d - boards/platforms: update xilinx programmers. <Florent Kermarrec>
    * | | | | | 3c34039b - build/xilinx/vivado: ensure Vivado process our .xdc early. <Florent Kermarrec>
    |/ / / / /
    * | | | | b0578580 - gen/fhdl/verilog: explicitly define input/output/inout wires. <Florent Kermarrec>
    * | | | | 0aa3c339 - targets/genesys2: set cmd_latency to 1. <Florent Kermarrec>
    * | | | | 95b57899 - bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases). <Florent Kermarrec>
    * | | | | 98d1b451 - platforms/targets: fix CI. <Florent Kermarrec>
    * | | | | 22bcbec0 - boards: keep in sync with LiteX-Boards, integrate improvements. <Florent Kermarrec>
    * | | | | 28f85c74 - build/lattice/programmer: add UJProg (for ULX3S). <Florent Kermarrec>
    * | | | | 85ac5ef1 - build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer. <Florent Kermarrec>
    * | | | | 9a7f9cb8 - build/generic_programmer: catch 404 not found when downloading config/proxy. <Florent Kermarrec>
    * | | | | d0b8daa0 - build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request. <Florent Kermarrec>
    * | | | | b8f9f83a - build/openocd: add find_config method to allow using local config file or download it if not available locally. <Florent Kermarrec>
    * | | | | 9bef218a - cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt). <Florent Kermarrec>
    * | | | |   6f24d46d - Merge pull request #496 from gsomlo/gls-fix-makefiles <enjoy-digital>
    |\ \ \ \ \
    | * | | | | edfed4f0 - software/*/Makefile: no need to copy .S files from CPU directory <Gabriel Somlo>
    |/ / / / /
    * | | | |   7f8e34c6 - Merge pull request #494 from shuffle2/patch-2 <enjoy-digital>
    |\ \ \ \ \
    | * | | | | ee413527 - diamond: quiet warning about missing clkin freq for EHXPLLL <shuffle2>
    |/ / / / /
    * | | | | 07e0153b - CHANGES: update. <Florent Kermarrec>
    * | | | | 21127031 - cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple. <Florent Kermarrec>
    * | | | | c06a1279 - cpu/microwatt: add pythondata and fix build with it. <Florent Kermarrec>
    * | | | | 45377d9f - cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width. <Florent Kermarrec>
    * | | | | 7c69a6db - bios/cmd_mdio.c:  fix missing <base/mdio.h> import. <Florent Kermarrec>
    * | | | | b0205335 - cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c. <Florent Kermarrec>
    * | | | | 97e534d0 - cpus: add nop instruction and use it to simplify the BIOS. <Florent Kermarrec>
    * | | | | 4efc7835 - cpus: add human_name attribute and use it to simplify the BIOS. <Florent Kermarrec>
    * | | | | d81f171c - software/libbase/system.c: remove unused includes. <Florent Kermarrec>
    * | | | |   3bbadb35 - Merge pull request #492 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \ \ \
    | * \ \ \ \   999b93af - Merge branch 'master' into blackparrot_litex <enjoy-digital>
    | |\ \ \ \ \
    | |/ / / / /
    |/| | | | |
    * | | | | |   705d3887 - Merge pull request #474 from fjullien/term_hist_auto_compl <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | 74dc444b - bios: add auto completion for commands <Franck Jullien>
    | * | | | | | fc2b8226 - bios: switch command handler to a modular format <Franck Jullien>
    | * | | | | | 86cab3d3 - bios: move helper functions to their own file <Franck Jullien>
    | * | | | | | bc5a1986 - bios: add terminal history <Franck Jullien>
    | * | | | | | e764eabd - builder: add a parameter to pass options to BIOS Makefile <Franck Jullien>
    | | * | | | | 0c770e06 - Update README.md <Sadullah Canakci>
    | | * | | | | 19bb1b9b - update to comply with python-data layout <sadullah>
    | | * | | | | 3eb9efd6 - BP fpga recent version <sadullah>
    | | * | | | | bf864d33 - Fix memory transducer bug, --with-sdram for BIOS works, memspeed works <sadullah>
    | | * | | | | cf01ea65 - rebased, minor changes in core.py <sadullah>
    | | * | | | | b7b9a1f0 - Linux works, LiteDRAM works (need cleaning, temporary push) <sadullah>
    | | * | | | | 74140587 - Create GETTING STARTED <Sadullah Canakci>
    | |/ / / / /
    |/| | | | |
    * | | | | |   e853cac6 - Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | a11f1c39 - Removed erase flag and made progress output less noisy <Ilya Epifanov>
    | | |_|_|/ /
    | |/| | | |
    * | | | | |   a6779b9d - Merge pull request #491 from gsomlo/gls-spisd-clusters <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | c8e3bba4 - software: spisdcard: cosmetic: avoid filling screen with cluster numbers <Gabriel Somlo>
    * | | | | | | b5978b21 - .travis.yml: disable python3.5 test (nMigen requires 3.6+). <Florent Kermarrec>
    * | | | | | | 10371a33 - CHANGES: update. <Florent Kermarrec>
    * | | | | | | bd8a4100 - cpu/minerva: add pythondata and use it to compile the sources. <Florent Kermarrec>
    * | | | | | | e4a4659d - litex_setup: add nmigen dependency (used to generate Minerva CPU). <Florent Kermarrec>
    * | | | | | | d3e3ca06 - CHANGES: start listing changes for next release. <Florent Kermarrec>
    |/ / / / / /
    * | / / / / 3c70c83f - cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs. <Florent Kermarrec>
    | |/ / / /
    |/| | | |
    * | | | | bb70a232 - cpu/software: move CPU specific software from the BIOS to the CPU directories. <Florent Kermarrec>
    * | | | | 0abc7d4f - cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository. <Florent Kermarrec>
    * | | | | b82b3b7e - integration/soc: rename usb_cdc to usb_acm. <Florent Kermarrec>
    * | | | | 0a1afbf6 - litex/__init__.py: remove retro-compat > 6 months old. <Florent Kermarrec>
    * | | | | 3531a641 - soc: allow passing custom CPU class to SoC. <Florent Kermarrec>
    | | | * | 83f4dcb2 - Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv <Ilya Epifanov>
    | | |/ /
    | |/| |
    | | | * 64b50515 - Add RDIMM side-B inversion support <David Shah>
    | |_|/
    |/| |
    * | |   90a6343d - Merge pull request #488 from enjoy-digital/python3.5 <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 9941e4c1 - travis: add back test on python3.5 (python3.6 is recommended but we can try to keep 3.5 compatibility until we have good reason to no longer support it). <Florent Kermarrec>
    |/ /
    * |   855d614e - Merge pull request #481 from betrusted-io/unfstringify <enjoy-digital>
    |\ \
    | * | 17b76654 - propose patch to not break litex for python 3.5 <bunnie>
    |/ /
    * | 56aa7897 - create first release, add CHANGES and note about Python modules in README. <Florent Kermarrec>
    * | 6d0896de - cpu/serv: switch to pythondata package instead of local git clone. <Florent Kermarrec>
    * | 1b069268 - README: update Python minimal version to 3.6. <Florent Kermarrec>
    * | ff61b1f6 - litex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX data. <Florent Kermarrec>
    * |   4d86ab9d - Merge pull request #399 from mithro/litex-sm2py <enjoy-digital>
    |\ \
    | * \   317ea7ed - Merge branch 'master' into litex-sm2py <enjoy-digital>
    | |\ \
    | * | | 1f356695 - litex_sim: Find tapcfg from pythondata module. <Tim 'mithro' Ansell>
    | * | | 3aee8a52 - Remove directories from submodules from MANIFEST.in file. <Tim 'mithro' Ansell>
    | * | | ebcb2a44 - Rename litex-data-XXX-YYY to pythondata-XXX-YYY <Tim 'mithro' Ansell>
    | * | | a39a4ec2 - Only allow fast-forward pulls. <Tim 'mithro' Ansell>
    | * | | e618d41f - Fixing mor1kx data finding. <Tim 'mithro' Ansell>
    | * | | 2e3b7f20 - Fix typo in error message. <Tim 'mithro' Ansell>
    | * | | 83b25813 - Fix the libcompiler_rt path. <Tim 'mithro' Ansell>
    | * | | 1c1c5bcb - Remove submodules. <Tim 'mithro' Ansell>
    | * | | c96d1e66 - Fix import for data. <Tim 'mithro' Ansell>
    | * | | 119985f3 - Use the current directory you are running. <Tim 'mithro' Ansell>
    | * | | 69367f8d - Make litex a namespace. <Tim 'mithro' Ansell>
    | * | | 3ae4f8f2 - Adding missing vexriscv CPU. <Tim 'mithro' Ansell>
    | * | | ac3fd794 - Adding missing comma. <Tim 'mithro' Ansell>
    | * | | 3df6c0c8 - Adding litex-data-software-compiler_rt as a required package. <Tim 'mithro' Ansell>
    | * | | 3964565e - Fixed quotes in `litex_setup.py` <Tim 'mithro' Ansell>
    | * | | d5a21a75 - Converting litex to use Python modules. <Tim 'mithro' Ansell>
    |  / /
    * | | 5ef869b9 - soc/cpu: add memory_buses to cpus and use them in add_sdram. <Florent Kermarrec>
    * | | 467fee3e - soc/cpu: rename cpu.buses to cpu.periph_buses. <Florent Kermarrec>
    |/ /
    * |   05815c4e - Merge pull request #477 from shuffle2/patch-1 <enjoy-digital>
    |\ \
    | * | f71014b9 - diamond: fix include paths <shuffle2>
    |/ /
    * | 4dece4ce - soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). <Florent Kermarrec>
    * |   c5ef9c73 - Merge pull request #473 from fjullien/memusage <enjoy-digital>
    |\ \
    | * | 3892d7a9 - bios: print memory usage <Franck Jullien>
    * | | 9460e048 - tools/litex_sim: use similar analyzer configuration than wiki. <Florent Kermarrec>
    * | |   443cc72d - Merge pull request #476 from enjoy-digital/serv <enjoy-digital>
    |\ \ \
    | * | | 1d1a4ecd - software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning. <Florent Kermarrec>
    | * | | fb9e369a - serv: connect reset. <Florent Kermarrec>
    | * | | 71778ad2 - serv: update copyrights (Greg Davill found the typos/issues). <Florent Kermarrec>
    | * | | 1f9db583 - serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :). <Florent Kermarrec>
    | * | | 2efd939d - serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill). <Florent Kermarrec>
    | * | | 22c39236 - initial SERV integration. <Florent Kermarrec>
    | | |/
    | |/|
    * | | c4c891de - build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis). <Florent Kermarrec>
    * | |   192849f0 - Merge pull request #475 from gregdavill/read_verilog_defer <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | 642c4b30 - build/trellis: add verilog_read -defer option to yosys script <Greg Davill>
    |/ /
    * | 96e7e6e8 - bios/sdram: reduce number of scan loops during cdly scan to speed it up. <Florent Kermarrec>
    * | 43e1a5d6 - targets/kcu105: use cmd_latency=1. <Florent Kermarrec>
    * | 85a059bf - bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal. <Florent Kermarrec>
    * | 038e1bc0 - targets/kc705: manual DDRPHY_CMD_DELAY no longer needed. <Florent Kermarrec>
    * | aaed4b94 - bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle. <Florent Kermarrec>
    * |   33c7b2ce - Merge pull request #472 from antmicro/jboc/sdram-calibration <enjoy-digital>
    |\ \
    | * | ab92e81e - bios/sdram: add automatic cdly calibration during write leveling <Jędrzej Boczar>
    * | |   4608bd18 - Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | b0f8ee98 - litex_sim: add option to create SDRAM module from SPD data <Jędrzej Boczar>
    * | | 0b3c4b50 - soc/cores/spi: add optional aligned mode. <Florent Kermarrec>
    * | | 6bb22dfe - cores/spi: simplify. <Florent Kermarrec>
    * | | fc434af9 - build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt). <Florent Kermarrec>
    * | | 1457c320 - xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale. <Florent Kermarrec>
    * | | 69462e66 - build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input. <Florent Kermarrec>
    * | | 65e6ddc6 - lattice/common: add LatticeECP5DDRInput. <Florent Kermarrec>
    * | | 2031f280 - lattice/common: cleanup instances, simplify tritates. <Florent Kermarrec>
    * | | 2d25bcb0 - lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput. <Florent Kermarrec>
    | |/
    |/|
    * | 56e15284 - platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. <Florent Kermarrec>
    * | 08e4dc02 - tools/remote/etherbone: update import. <Florent Kermarrec>
    |/
    * 19f983c4 - targets: manual define of the SDRAM PHY no longer needed. <Florent Kermarrec>
    * c0f3710d - bios/sdram: update/simplify with new exported LiteDRAM parameters. <Florent Kermarrec>
    * 3915ed97 - litex_sim: add phytype to PhySettings. <Florent Kermarrec>
    * c0c5ae55 - build/generic_programmer: move requests import to do it only when needed. <Florent Kermarrec>
    * c9ab5939 - bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4. <Florent Kermarrec>

 * litex-boards changed from cb95962 to 0b11aba
    * 0b11aba - platforms/nexys_video: add spisdcard pins. <Florent Kermarrec>
    * 76df4e3 - targets: simplify Ethernet/Etherbone integration on targets with both. <Florent Kermarrec>
    * 2e1a816 - pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone. <Florent Kermarrec>
    *   33fe308 - Merge pull request #78 from antmicro/jboc/spd-read <enjoy-digital>
    |\
    | * e5578a1 - zcu104/platform: change I2C number to 0 <Jędrzej Boczar>
    | * ac1f1cd - zcu104: add I2C <Jędrzej Boczar>
    * | 71f220a - colorlight_5a_75b: remove unnecessary parenthesis. <Florent Kermarrec>
    * | 2f3817c - pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst. <Florent Kermarrec>
    * | f19bc36 - pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer. <Florent Kermarrec>
    * | d6518c7 - prog/openocd: fix openocd_xc6 cfgs. <Florent Kermarrec>
    * | 22f18f6 - pano_logic_g2: move gmii_rst_n to _CRG. <Florent Kermarrec>
    * |   935a711 - Merge pull request #77 from skiphansen/master <enjoy-digital>
    |\ \
    | * | 0648c04 - Updated comment, added link to clocking documentation. <Skip Hansen>
    | * | 1ab4656 - Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200) <Skip Hansen>
    |/ /
    * | 9b572ec - forest_kitten_33: add minimal target and use es1. <Florent Kermarrec>
    * |   7ad0363 - Merge pull request #76 from gsomlo/gls-nexys4-spisdcard <Tim Ansell>
    |\ \
    | * | 435913f - platforms/nexys4ddr: add option to build with spi-mode sdcard support <Gabriel Somlo>
    |/ /
    * | 0d549a8 - platforms: add forest_kitten_33 initial platform suppport. <Florent Kermarrec>
    * | 12b54a7 - platforms/alveo_u250: add clk300 clock constraints. <Florent Kermarrec>
    * | 46f78b5 - nexys_video: add usb_fifo pins. <Florent Kermarrec>
    * | 445338e - platforms/nexys_video: add specific openocd cfg (use channel 1). <Florent Kermarrec>
    * | 5aeb7d8 - targets/acorn_cle_215: fix typo in description. <Florent Kermarrec>
    * | eeba64d - targets: use soc.build_name in load/flash bitstream. <Florent Kermarrec>
    * | 76551de - platforms/nexys_video: add sdcard pins, move clk/rst to top. <Florent Kermarrec>
    * | 83457b8 - platforms/arty: add _sdcard_pmod_io. <Florent Kermarrec>
    * | 8158d94 - targets/c10lprefkit: switch to litehyperbus. <Florent Kermarrec>
    * | 587caf7 - paltforms/marblemini: add break_off_pmod. <Florent Kermarrec>
    * | c2cd863 - platforms/ecp5_evn: rename spiflash1x to spiflash, rewrite hardware/configuration description and remove make_spiflash. <Florent Kermarrec>
    * |   3f0f120 - Merge pull request #70 from ilya-epifanov/ecp5-evn-spi1x-and-flash-params <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 0ba8045 - Added spiflash1x pins, a method to create an SpiFlash instance and a note on a second UART channel of FT2232H <Ilya Epifanov>
    * | b9ee3a7 - alveo_u250: re-organize the auto-generated IOs, add build/load parameters. <Florent Kermarrec>
    * | c0b7afc - targets/alveo_u250: +x. <Florent Kermarrec>
    * | 67d2a49 - tools/extract_xdc_pins: +x. <Florent Kermarrec>
    * | 482d7a6 - targets/pcie: use 128-bit datapath and 8 max_pending_requests on pcie_x4 configurations. <Florent Kermarrec>
    * | 2bb7fce - targets/acorn_cle_215: add minimal instructions to reproduce the results. <Florent Kermarrec>
    * |   6757c4e - Merge pull request #71 from daveshah1/alveo_u250 <enjoy-digital>
    |\ \
    | * | 088ccec - Add Alveo U250 platform and target <David Shah>
    | |/
    * | c7404e3 - targets/acorn_cle_215: switch to MT41K512M16 (Acorn has a 1GB DDR3 vs 512MB on NiteFury). <Florent Kermarrec>
    * | d05b10f - target/camlink_4k: add missing import. <Florent Kermarrec>
    * | b211c43 - test/test_targets: add acorn_cle_215 and marblemini. <Florent Kermarrec>
    * | 4faa91c - platforms/marblemini: review/cleanup. <Florent Kermarrec>
    * |   4ffdcb5 - Merge pull request #75 from jersey99/marblemini <enjoy-digital>
    |\ \
    | * | e4ccfcf - platforms/marblemini.py: Cleanup. Add openocd for programming marblemini <Vamsi K Vytla>
    | * |   a7d6de7 - Merge branch 'master' into marblemini <Vamsi K Vytla>
    | |\ \
    | * | | 5f7f087 - community/platforms/marblemini.py: Added marblemini from https://github.com/berkeleylab/marble-mini/ <Vamsi K Vytla>
    |  / /
    * | | 6f22f08 - targets: add LedChaser on platforms with user_leds. <Florent Kermarrec>
    * | |   b9a0f23 - Merge pull request #74 from tommythorn/master <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 6335717 - targets/orangecrab.py: propagate command arguments <Tommy Thorn>
    * | | 19b12fd - targets/panol_logic_g2: replace with a minimal target. <Florent Kermarrec>
    * | | 99c0435 - platforms/pano_logic_g2: simplify/cleanup. <Florent Kermarrec>
    * | | 6b5492a - pano_logic_g2: add copyrights. <Florent Kermarrec>
    * | | 6ddd859 - add pano_logic_g2 from litex-buildenv. <Florent Kermarrec>
    * | | 27c242b - targets/pcie: switch to PCIe X4 on all boards that support it. <Florent Kermarrec>
    * | | f993953 - targets/pcie: update LitePCIe constraints. <Florent Kermarrec>
    |/ /
    * | d34c3ba - prog: use different openocd config files for FT232/FT2232. <Florent Kermarrec>
    * | 117d1a1 - prog: add colorlight_5a_75b openocd config. <Florent Kermarrec>
    * | e500d90 - platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode. <Florent Kermarrec>
    * | 59e8c2c - acorn_cle_215: add .bin generation and --flash argument, working on hardware :). <Florent Kermarrec>
    * | a049fa6 - add Acorn CLE 215+ platform/target. <Florent Kermarrec>
    * | da61aab - targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets. <Florent Kermarrec>
    * | b58b9b9 - platforms: fix CI. <Florent Kermarrec>
    * | 2d9543b - targets: add build/load parameters on all targets. <Florent Kermarrec>
    * | 19eb570 - platforms: make sure all traditional platforms have a create_programmer method. <Florent Kermarrec>
    * | 84468c2 - targets/CRG: platforms are now automatically constraining the input clocks. <Florent Kermarrec>
    * | 1f88a9d - platforms: make sure clocks inputs are constraints on all platforms. <Florent Kermarrec>
    * | 86648ec - platforms/vcu118: rename ddram_second_channel to ddram:1. <Florent Kermarrec>
    * | e1820c7 - platforms/ac701: indent HPC. <Florent Kermarrec>
    * | 2129b67 - platforms: make sure all plarforms have separators. <Florent Kermarrec>
    * | ea0eda9 - platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series. <Florent Kermarrec>
    * | 588bbac - add prog directory with some Xilinx OpenOCD configurations files. <Florent Kermarrec>
    * | 78b5727 - targets: rename usb_cdc to usb_acm. <Florent Kermarrec>
    |/
    * 2213d73 - targets/kcu105: use cmd_latency=1. <Florent Kermarrec>
    * a8a42c5 - targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed. <Florent Kermarrec>
    * 865b01e - ecpix5: add ethernet. <Florent Kermarrec>
    * 6fe4c4e - ecpix5: add DDR3 (working) <Florent Kermarrec>
    * efb13bc - add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working. <Florent Kermarrec>
    * 4154bdf - targets/PCIe: add PCIe software reset. <Florent Kermarrec>
    * 4ad6042 - platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. <Florent Kermarrec>
    * 4185a01 - targets: manual define of the SDRAM PHY is no longer needed. <Florent Kermarrec>

 * migen changed from 0.6.dev-337-g19d5eae to 0.6.dev-347-gb1b2b29
    * b1b2b29 - zc706: redo FMC connectors <Astro>
    * 0d16e03 - kasli: add DCXO pins <Sebastien Bourdeauducq>
    * ea1eefe - zc706: add FMC HPC connector HA pins <Astro>
    * dc9cfe6 - kasli2: add upper EEMs <Sebastien Bourdeauducq>
    * 6809ee0 - kasli2: add cdr_clk and cdr_clk_clean <Sebastien Bourdeauducq>
    * afc6b02 - zc706: fix LAxx_CC pin naming consistency with KC705 <Sebastien Bourdeauducq>
    * 0762612 - zc706: add user_sma_clock <Sebastien Bourdeauducq>
    * e71f21e - zc706: add FMC connectors <Astro>
    * 5b5e4fd - kasli: typo <Sebastien Bourdeauducq>
    * bea0bdc - kasli: v2.0 support (WIP) <Sebastien Bourdeauducq>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 d62fd24c81c54dae6eb7f06092316215b73237ad litedram (2020.04-43-gd62fd24)
 0feed1720d0063ff67210728ecfe422891f809e0 liteeth (2020.04-7-g0feed17)
 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04)
 b0e8383d6179ee81a708204d4db9263d6fadc6c8 litepcie (2020.04-12-gb0e8383)
 2e5c5b12d52f695f4560ca7dd08b4170d7568715 litesata (2020.04)
 54488c0f4d6e9e953f1a0de3d578915a5e4ccddf litescope (2020.04)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
 77139289f86a412deb0da7f783ea44ded5e05900 litex (2020.04-260-g77139289)
 0b11aba8a18a9e38f6a49e7f291c072e80e3224e litex-boards (2020.04-71-g0b11aba)
 7da392963878842f93f09a7a218c1052ae5e45d6 litex-renode (remotes/origin/HEAD)
 b1b2b298b85a795239daad84c75be073ddc4f8bd migen (0.6.dev-347-gb1b2b29)
 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this issue Jun 29, 2020
@mateusz-holenko
Updating submodules.
6e053cf 
 * litedram changed from de55a8e to 9044c10
    * 9044c10 - phy/ecp5ddrphy: use sys_rst instead of sys2x_rst as reset on primitives and do sys2x reset externally. <Florent Kermarrec>
    * fa7d91a - phy/ecp5: simplify/fix dqs_oe/dq_oe and revert BitSlip on dq_i_data. <Florent Kermarrec>
    *   8c112c7 - Merge pull request #207 from ozbenh/sim-autoinit <enjoy-digital>
    |\
    | * 4580882 - dfii: Really default to HW control <Benjamin Herrenschmidt>
    |/
    * 52d7dbe - frontend/fifo: make sure FIFO is only used on LiteDRAMNativePort, expose writer/reader fifo depth, add separators and update copyrights. <Florent Kermarrec>
    *   c4c8803 - Merge pull request #204 from antmicro/jboc/spd-read <enjoy-digital>
    |\
    | * 863c45a - test/spd_data: add missing files to tracking <Jędrzej Boczar>
    | * cbd9087 - modules/spd: select tFAW_min_ck depending on page size <Jędrzej Boczar>
    | * a8f2c04 - modules: add DDR4SPDData parser <Jędrzej Boczar>
    * |   067e8a5 - Merge pull request #205 from antmicro/jboc/fifo <enjoy-digital>
    |\ \
    | * | e5179eb - gen: fix LiteDRAMFIFO parameters <Jędrzej Boczar>
    | * | 8fedc3f - frontend/fifo: increase FIFO level after data has actually been written <Jędrzej Boczar>
    |/ /
    * | 992f80c - litedram_gen: add Ultrascale(+) support and KCU105 config file, remove cmd_delay on 7-series (not automatically calibrated). <Florent Kermarrec>
    * | 361d250 - litedram_gen: avoid second S7PLL for iodelay clk, generate it from main S7PLL on CLKOUT0 (with fractional divide). <Florent Kermarrec>
    * | 1b56dcf - litedram_gen: add more memtype asserts, remove csr_alignment (now fixed to 32-bit). <Florent Kermarrec>
    * | a595fe0 - dfii: simplify control using CSRFields. <Florent Kermarrec>
    * |   899462c - Merge pull request #202 from ozbenh/sim-autoinit <enjoy-digital>
    |\ \
    | * | f3f89ed - Default to HW control for sim <Benjamin Herrenschmidt>
    * | |   d62fd24 - Merge pull request #201 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \ \
    | |/ /
    |/| /
    | |/
    | * 4233f86 - modules/spd: save SPD data in SDRAMModule to allow for runtime verification <Jędrzej Boczar>
    * | f23cb80 - litedram_gen: revert builder.build(..., regular_comb=False). <Florent Kermarrec>
    * | d1db115 - litedram_gen: review/simplify #197. <Florent Kermarrec>
    * |   a8e281f - Merge pull request #197 from ozbenh/standalone-sim <enjoy-digital>
    |\ \
    | * | d0f0c94 - phy/model: Don't generate empty mem_*.init files <Benjamin Herrenschmidt>
    | * | b8d6da5 - gen: Allow generation of a standalone sim model <Benjamin Herrenschmidt>
    * | |   83b9a1d - Merge pull request #199 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \ \
    | |/ /
    |/| /
    | |/
    | * cbe91bc - modules: add function for parsing SPD EEPROM dumps from BIOS firmware <Jędrzej Boczar>
    * | 639a31f - test/test_timing: update test_txxd_controller. <Florent Kermarrec>
    * | 3c1ab76 - litedram/common/tXXDController: only set reset to 1 when txxd is None. <Florent Kermarrec>
    |/
    *   e95af3f - Merge pull request #195 from enjoy-digital/bios-libs <enjoy-digital>
    |\
    | * fe48a92 - test/reference: update. <Florent Kermarrec>
    | * c30910a - init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS. <Florent Kermarrec>
    |/
    * 5078b19 - core/crossbar: remove retro-compat > 6 months old. <Florent Kermarrec>
    * 3b105d5 - modules: fix SDRAMRegisteredModule. <Florent Kermarrec>
    *   b2a5685 - Merge pull request #189 from daveshah1/ddr4_rdimm_init <enjoy-digital>
    |\
    | * 70054ba - Add support for DDR4 RDIMMs <David Shah>
    * | 7ae4ad5 - modules: add SDR/DDR/DDR2/DDR3/DDR4 SDRAMModule (and Registered versions). <Florent Kermarrec>
    * | 1f7d9eb - litedram_gen: pass FPGA speedgrade to iodelay_pll. <Florent Kermarrec>
    * | f4871b9 - litedram_gen: use default settings on wb_bus. <Florent Kermarrec>
    * | 6fb8396 - litedram_gen: remove csr_base (no longer needed since CPUNone type will automatically set csr mapping to 0x00000000) and create a use bus with the same address_width as the main bus of the SoC. <Florent Kermarrec>
    * | 94c215e - litedram_gen: review/simplify #193, always add ddrctrl. <Florent Kermarrec>
    * |   f036ec2 - Merge pull request #193 from ozbenh/standalone-cores <enjoy-digital>
    |\ \
    | * | 04717b4 - gen: Rename standalone core wishbone <Benjamin Herrenschmidt>
    | * | b0838f7 - gen: Add option to specify CSR alignment <Benjamin Herrenschmidt>
    | * | d5a03b3 - gen: Add option to generate DDRCTL on standalone cores <Benjamin Herrenschmidt>
    | * | efad6b3 - gen: Add option to specify CSR base for standalone cores <Benjamin Herrenschmidt>
    | * | c91cbb5 - gen: Remove obsolete bus_expose config option <Benjamin Herrenschmidt>
    |/ /
    * | 4e539ad - litedram_gen: switch to SoCCore. <Florent Kermarrec>
    * | ac33d29 - litedram_gen: simplify and expose bus when CPU is set to None. <Florent Kermarrec>
    * | fe47838 - litedram_gen: expose a Bus Slave port instead of a CSR port. <Florent Kermarrec>
    * | 52b49fb - test/reference: update. <Florent Kermarrec>
    * | 52ca393 - modules: add MT41J512M16/MT41K512M16. <Florent Kermarrec>
    * | 589957f - phy: extend Bitslip capability to 2 sys_clk cycles. <Florent Kermarrec>
    * | 5c0231d - common/BitSlip: add cycles parameter to extend bitstlip to multiple system clock cycles. <Florent Kermarrec>
    * | ed0810a - gen: Optionally pass cpu_variant from YAML to SoC <Benjamin Herrenschmidt>
    |/
    *   dfe6f90 - Merge pull request #188 from daveshah1/ddr4_dimm_x4 <enjoy-digital>
    |\
    | * 5b4381b - usddrphy: Support for x4 chip based DIMMs <David Shah>
    * |   9f136c0 - Merge pull request #187 from daveshah1/add_MTA18ASF2G72PZ <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 97f0a37 - modules: Add MTA18ASF2G72PZ DDR4 RDIMM <David Shah>
    |/
    * 9a2d3f0 - common: add PHYPadsReducer to only use specific DRAM modules. <Florent Kermarrec>
    * 20a849c - test/reference: update ddr4_init.h <Florent Kermarrec>
    *   cec3a99 - Merge pull request #181 from antmicro/jboc/eeprom-timings <enjoy-digital>
    |\
    | * 312bce2 - modules: pass rate automatically when creating module from SPD data <Jędrzej Boczar>
    | * 07bbd79 - modules: update existsing SO-DIMM timings based on SPD data <Jędrzej Boczar>
    | * cf83ac6 - test: improve SPD tests of Micron DDR3 SO-DIMM modules <Jędrzej Boczar>
    | * 854a614 - modules: fix calculations of speedgrade from tck in SPD data <Jędrzej Boczar>
    | * c744204 - modules: fix nrows in MT8KTF51264 <Jędrzej Boczar>
    | * 3980e06 - modules: add option to load module parameters from SPD data <Jędrzej Boczar>
    * | 48c2fc2 - phy: simplify/improve dqs preamble/postamble. <Florent Kermarrec>
    * | eaf0691 - phy/ecp5ddrphy: simplify, working with dqs preamble/postamble. <Florent Kermarrec>
    * | 12a017f - phy/ecp5ddrphy: simplify/cleanup. <Florent Kermarrec>
    * | 62915cd - phy: rework BitSlip to simplify integration, add DQSPattern module. <Florent Kermarrec>
    * | 9ff9e82 - phy/usddrphy: move pads.ten control to control block. <Florent Kermarrec>
    * | 91a9a2a - phy/ecp5ddrphy: fix dqs preamble/postamble control. (make it similar to 7-series/Ultrascale). <Florent Kermarrec>
    * | 5d29686 - phy/s7ddrphy/usddrphy: more compact write dqs postamble/preamble control path. <Florent Kermarrec>
    * | 8d0e7f6 - phy/usddrphy: simplify/cleanup write control path/dqs postamble/preamble control path. <Florent Kermarrec>
    * | 57b16c2 - phy/usddrphy: simplify/cleanup write control path, add DQS Pre/Postamble support. <Florent Kermarrec>
    * | 1462a43 - phy/usddrphy: cleanup/simplify read control path. <Florent Kermarrec>
    * | cd671f9 - phy/s7ddrphy: cleanup/simplify read control path. <Florent Kermarrec>
    * | d061e60 - test/reference: update. <Florent Kermarrec>
    * | 45a03df - phy/init: add phytype to PhySettings and export more parameters to C header to simplify software. <Florent Kermarrec>
    * | 2df9004 - init: improve ident. <Florent Kermarrec>
    * | eca7fc2 - phy/ecp5ddrphy: remove Bitslip from comment (no longer present). <Florent Kermarrec>
    * | f4f2948 - phy/ecpddrphy: remove Bitslip (not used and redundant with dqs_read) and use BitSlip software control to move dqs_read. <Florent Kermarrec>
    * | e2b4c2b - phy/ecp5ddrphy: cosmetics. <Florent Kermarrec>
    |/
    * f68f1dd - phy/ecp5ddrphy/control: cleanup/simplify and document (no functional changes). <Florent Kermarrec>
    * fdf7c76 - phy/control: cleanup/simplify (no functional changes). <Florent Kermarrec>
    * a767618 - phy: improve flow control readability (add separators between Read/Write/Write DQS Postamble/Preamble parts). <Florent Kermarrec>

 * liteeth changed from 705003e to dbe15f1
    *   dbe15f1 - Merge pull request #42 from shuffle2/padding <enjoy-digital>
    |\
    | * d66d302 - mac padding: fix counter reset value <Shawn Hoffman>
    |/
    * b1bcfb2 - mac/LiteEthMACCoreCrossbar: remove unnecessary fifos. <Florent Kermarrec>
    * 8e11857 - common: remove Port.connect and use 2 separate Record.connect. <Florent Kermarrec>
    * 17caf17 - mac/LiteEthMACCoreCrossbar: remove cpu_dw. <Florent Kermarrec>
    * 23b420a - mac/LiteEthMAC: simplify hybrid mode and avoid some duplication. <Florent Kermarrec>
    * 51cd546 - core/mac: add missing separators, fix typos. <Florent Kermarrec>
    * 59d3336 - mac: add separators, improve indent, minor simplifications. <Florent Kermarrec>
    * d06c7b4 - frontend: add separators, improve indent, minor simplifications. <Florent Kermarrec>
    * 2d58f48 - core: improve indent. <Florent Kermarrec>
    * c262818 - core: add separators. <Florent Kermarrec>
    * bb29706 - core: remove mac retro-compatibility (>6 months old). <Florent Kermarrec>
    * 0feed17 - phy/gmii/CRG: add BUFG on RX and do the TX clock Mux with combinatorial logic (from @skiphansen initial work). <Florent Kermarrec>
    * 53c9eb9 - core/ip: move mcase_oui/ip_mask definition to common and set target_mac with NextValue. <Florent Kermarrec>
    *   58e1681 - Merge pull request #41 from shuffle2/mcast <enjoy-digital>
    |\
    | * 6d00ec1 - iptx: support multicast mac and bypass arp table <Shawn Hoffman>
    * | 8afdec9 - phy/ecp5rgmii: review/simplify inband_status integration. <Florent Kermarrec>
    * |   55af430 - Merge pull request #40 from shuffle2/master <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 26c4e41 - ecp5rgmii: enable reading inband PHY_status <Shawn Hoffman>
    |/
    * dc67e6d - phy/ecp5rgmii: use DDROutput/DDRInput now available for ECP5. <Florent Kermarrec>

 * litepcie changed from 586ef78 to 61c202d
    * 61c202d - litepcie_gen: allow up to 32 user IRQs with MSI-X. <Florent Kermarrec>
    * 9e84d6a - litepcie_gen: remove flash_ios. <Florent Kermarrec>
    * 3f63e74 - core/msi/LitePCIeMSIX: use width in enable/pba CSRs. <Florent Kermarrec>
    * 2274b88 - litepcie_gen: expose stream's first on AXI interface as tuser. <Florent Kermarrec>
    *   3271597 - Merge pull request #32 from sergachev/master <enjoy-digital>
    |\
    | * 9c5d250 - example: fix phy type <Ilia Sergachev>
    |/
    * 761f8fb - example: uniformize kc705/kcu105 examples. <Florent Kermarrec>
    * c84605e - litepcie_gen: add Ultrascale support and example on kcu105.yml. <Florent Kermarrec>
    * b73b72e - examples/kcu105: cleanup, use 4 lanes. <Florent Kermarrec>
    * 597ab2d - README: add MSI/MSI-X support. <Florent Kermarrec>
    * 150b34e - core/msi: test and fix LitePCIeMSIX, add register on S7PCIEPHY to get MSI-X enable status. <Florent Kermarrec>
    * 4f8c624 - test/test_examples: update. <Florent Kermarrec>
    * 84c9d71 - core/msi: add initial MSI-X implementation (untested). <Florent Kermarrec>
    * 3ef2ae7 - software/kernel/main: add MSI Multi-Vector minimal support. <Florent Kermarrec>
    * bd375da - litepcie_gen: use generate_litepcie_software_headers. <Florent Kermarrec>
    * bf4b23c - software/generate_litepcie_software_header: add kernel to dst in generate_litepcie_software. <Florent Kermarrec>
    * 3a7a76b - examples: use generate_litepcie_software. <Florent Kermarrec>
    * ad93d52 - software: add generate_litepcie_software_headers/software functions to avoid duplication in targets. <Florent Kermarrec>
    * 8534965 - litepcie/software: add copy_litepcie_software function (to easily get litepcie software from targets). <Florent Kermarrec>
    *   5533144 - Merge pull request #30 from enjoy-digital/new_driver <enjoy-digital>
    |\
    | *   2703b8a - merge master. <Florent Kermarrec>
    | |\
    | |/
    |/|
    * | b0e8383 - frontend/dma/LitePCIeDMAReader: immediately return to IDLE state when disabled. <Florent Kermarrec>
    * |   4e333cb - Merge pull request #29 from sergachev/master <enjoy-digital>
    |\ \
    | * | 8192494 - kernel: remove unnecessary call to pci_release_regions() on device remove <Ilia Sergachev>
    |/ /
    * | c2fd143 - phy/s7pciephy: expose disable_constraints parameter to use_external_hard_ip. <Florent Kermarrec>
    | * 2658ce0 - software/kernel: replace remaining printk with pr_debug or dev_info and use dev_err instead of pr_err when possible. <Florent Kermarrec>
    | * a78a248 - software/kernel: replace printk(KERN_INFO with pr_debug for debug messages. <Florent Kermarrec>
    | * 79e448e - software/kernel: replace printk(KERN_ERR with pr_err. <Florent Kermarrec>
    | * 23f7045 - software: add #ifdef for optional peripheral support. <Florent Kermarrec>
    | * 1cae8cf - examples: update and more similarities with the integration in litex-boards. <Florent Kermarrec>
    | * 485a6c4 - software: import new driver. <Florent Kermarrec>
    | * c4c8705 - software: remove current driver. <Florent Kermarrec>
    |/
    * 6049a69 - litepcie_gen: add optional Sphinx/Html doc generation with --doc. <Florent Kermarrec>
    * 6bb89af - phy/s7pciehy: disable constraints generated from the .xci and use our owns. <Florent Kermarrec>
    *   ef7d40e - Merge pull request #28 from sergachev/master <enjoy-digital>
    |\
    | * 3eb2b86 - test_dma: remove unused imports and variables, fix mistypes <Ilia Sergachev>
    |/
    *   9a3ada5 - Merge pull request #27 from sergachev/master <enjoy-digital>
    |\
    | * e637090 - dma: fix another couple of mistypes <Ilia Sergachev>
    | * 4c4e3bf - dma: fix mistypes in comments <Ilia Sergachev>
    |/
    * 3ca6e38 - frontend/dma/monitor: reduce count_width from 32-bit (default) to 16-bit. <Florent Kermarrec>
    * 22faa07 - litepcie_gen: add pcie_data_width support. <Florent Kermarrec>
    *   96a6cdc - Merge pull request #25 from sergachev/master <enjoy-digital>
    |\
    | * 5804b43 - software: fix definitions <Ilia Sergachev>
    * 0496daf - litepcie_gen: add buffers on DMA sink/source to ensure data are clocked on LitePCIe interface and ease integration. <Florent Kermarrec>
    * 7818ace - frontend/dma: fix level CSRStatus size (+1). <Florent Kermarrec>
    * a85b1d7 - tlp/controller: expose cmp_bufs_buffered parameter. <Florent Kermarrec>
    * 264d7f3 - frontend/dma: allow asymetric writer/reader buffering depths. <Florent Kermarrec>
    * 9cb938e - frontend/dma: expose table_depth parameter. <Florent Kermarrec>
    * a6d836e - gen/examples: add software reset. <Florent Kermarrec>

 * litesata changed from 2e5c5b1 to b36d3a3
    * b36d3a3 - core/examples: update. <Florent Kermarrec>

 * litescope changed from 54488c0 to 15179cb
    * 15179cb - examples/targets/simple: update. <Florent Kermarrec>
    * 0e1ca9e - examples/make: update. <Florent Kermarrec>

 * litex changed from 2d018826 to 54598ed2
    * 54598ed2 - software/bios/Makefile: fix #578 merge. (get back #579). <Florent Kermarrec>
    * 7beffba1 - software/libbase/memtest: fix bus errors reporting. <Florent Kermarrec>
    *   ad76f5f3 - Merge pull request #578 from scanakci/blackparrot_litex <enjoy-digital>
    |\
    | *   eafceb94 - Merge branch 'master' into blackparrot_litex <enjoy-digital>
    | |\
    | |/
    |/|
    * |   5a1c3a7c - Merge pull request #579 from antmicro/fix_building_bios <enjoy-digital>
    |\ \
    | * | d72380c8 - Fix ordering of libraries <Mateusz Holenko>
    | | * caf520c8 - clean Makefile <sadullah>
    | | * 9256a4db - minor change in BP top module <sadullah>
    | | * 7c83a1b8 - syn with master blackparrot, upgrade BP to IMA <sadullah>
    | |/
    |/|
    * |   dae23f2a - Merge pull request #576 from betrusted-io/deprecate_slave <enjoy-digital>
    |\ \
    | * | 0b4c5059 - Deprecate slave terminology <bunnie>
    * | | 1e605fb2 - liblitesdcard/sdcard: update with litesdcard. <Florent Kermarrec>
    * | | 34e9d12e - interconnect/axi/AXIStreamInterface: add tuser support. <Florent Kermarrec>
    * | | 4094a6ec - liblitesdcard/sdcard: increase busy_wait and use common timeout. <Florent Kermarrec>
    * | | e8f84c96 - liblitesdcard/sdcard: decode cid only when SDCARD_DEBUG is set. <Florent Kermarrec>
    * | | c0770312 - liblitesdcard/sdcard_read: enable multiple block read. <Florent Kermarrec>
    * | | 8c572d2b - targets: add fixed sdcard clock on boards with SDCard support. <Florent Kermarrec>
    * | | c4669003 - software/bios/litesdcard: remove sdcard_set_clk. <Florent Kermarrec>
    * | | dfa3768d - integration/soc/add_sdcard: remove sdclk. <Florent Kermarrec>
    * | | 9a27465d - cores/clock/S6DCM: add expose_drp. <Florent Kermarrec>
    * | | d8aa9a42 - software/bios/boot: improve printfs. <Florent Kermarrec>
    * | | 55e01937 - software/libase/memtest: improve printfs and add progress bar on data test. <Florent Kermarrec>
    * | | 49741366 - libbase/progress: reduce to 40 HASHES_PER_LINE. <Florent Kermarrec>
    * | | 52d7f59a - software/liblitedram: remove DDRPHY_CMD_DELAY support (no longer useful). <Florent Kermarrec>
    * | | 07f145fd - software/liblitedram/sdram: remove SRAM hack. <Florent Kermarrec>
    * | | e2f9a825 - software/libbase/memtest: reorder functions. <Florent Kermarrec>
    |/ /
    * |   00d1118d - Merge pull request #575 from antmicro/jboc/memtest <enjoy-digital>
    |\ \
    | * | 3b084b28 - bios: move memtest from liblitedram to libbase <Jędrzej Boczar>
    |/ /
    * | 3a5aec69 - software/liblitesdcard: simplify, switch to DMAs, remove clocking/test functions. <Florent Kermarrec>
    * | fd4765e1 - integration/soc: replace SDDataReader/SDDataWriter with DMAs. <Florent Kermarrec>
    * | bc64e354 - soc/cores: add simple DMA with WishboneDMAReader/WishboneDMAWriter. <Florent Kermarrec>
    * | d7cc7d2a - platforms/genesys2: add usb_fifo. <Florent Kermarrec>
    * | 309eda42 - litex_term: keep and reduce inter-frame delay to 1e-5. <Florent Kermarrec>
    * | 64589cfd - soc/cores/uart/FT245: only use Asynchronous FIFO (Synchronous FIFO requires a software configuration). <Florent Kermarrec>
    * | 0780b629 - soc/cores/usb_fifo: cleanup and reduce fifo_depth (provide similar throughput when used as UART). <Florent Kermarrec>
    |/
    * 52b51e1e - CHANGES: update. <Florent Kermarrec>
    * d59cec5a - software: use a single crt0 (deprecate crt0-ctr/crt0-xip) and avoid unnecessary defines. <Florent Kermarrec>
    * 384646c6 - platforms/genesys2: use openocd_genesys2.cfg. <Florent Kermarrec>
    * e92efc1a - platforms/kcu105: add sdcard/spisdcard. <Florent Kermarrec>
    * 35b04658 - genesys2: add sdcard/spisdcard. <Florent Kermarrec>
    * d53a51c5 - platforms/netv2: add spisdcard. <Florent Kermarrec>
    * c8955864 - platforms/k705: rename mmc to sdcard and make it similar to other boards. <Florent Kermarrec>
    * 02908c51 - cpu/lm32: fix config include paths. <Florent Kermarrec>
    * b1fe3140 - bios/main: enable sdcardboot in boot_sequence with litesdcard. <Florent Kermarrec>
    * 847a5fcf - software/liblitesdcard/sdcard: boot with FatFs working (hacky). <Florent Kermarrec>
    * 5b2f9c24 - cores/cpu/microwatt: revert setup stack and fix missing subi  %r1,%r1,0x100 (thanks ozbenh). <Florent Kermarrec>
    * 0c0689f4 - wishbone/DownConverter: fix read datapath when access is skipped because sel = 0. <Florent Kermarrec>
    * 84617b58 - cores/cpu/microwatt: temporary revert crt0.S/setup stack. <Florent Kermarrec>
    *   e32e8c06 - Merge pull request #573 from ozbenh/bios-data <enjoy-digital>
    |\
    | * 28ea4b3f - software/microwatt: Fix copying data to RAM and clearing BSS <Benjamin Herrenschmidt>
    |/
    * 13e0852a - tools/litex_server: set socket option flags separately (required for Mac OS X). <Florent Kermarrec>
    * efa41fd6 - litex_sim: simplify a bit ethernet+etherbone. <Florent Kermarrec>
    * b0b37b4c - soc/cores/spi: make cs/loopback CSR optional. <Florent Kermarrec>
    * 05cb5f96 - bios/boot: rewrite ROM boot description. <Florent Kermarrec>
    *   bdcccb92 - Merge pull request #569 from gsomlo/gls-mor1kx-data-init <enjoy-digital>
    |\
    | * e96cfbbc - cpu/mor1kx: fix .data initialization (follow-up to PR #567) <Gabriel Somlo>
    * |   4cab38fa - Merge pull request #570 from gsomlo/gls-sdcard-lazy-init <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 9ad45a69 - liblitesdcard/[spi]sdcard: avoid redundant (re-)initialization <Gabriel Somlo>
    |/
    *   aa0cd213 - Merge pull request #565 from gsomlo/gls-cosmetic-spi-fat <enjoy-digital>
    |\
    | * 5d9d99c0 - liblitesdcard/sdcard: streamline initialization (cosmetic) <Gabriel Somlo>
    | * c05d0f19 - liblitesdcard/spisdcard: streamline initialization (cosmetic). <Gabriel Somlo>
    | * 7d5ca3f9 - bios/boot: addresses should use 'unsigned long' <Gabriel Somlo>
    * |   05d4756e - Merge pull request #567 from zyp/fix_data_segment <enjoy-digital>
    |\ \
    | * | 27fcddb2 - soc_core: Increase sram size default to 8k. <Vegard Storheil Eriksen>
    | * | 9c68d715 - bios/linker: Place .data in sram with initial copy in rom. <Vegard Storheil Eriksen>
    | * | 33689660 - bios/linker: Place .got in .rodata. <Vegard Storheil Eriksen>
    | |/
    * | b0f76112 - platforms/arty: move sdcard_pmod_io to JD. <Florent Kermarrec>
    * |   c3ed8025 - Merge pull request #568 from sergachev/master <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 3610b066 - build/sim/core/modules: fix compilation warnings <Ilia Sergachev>
    |/
    * 68d3804c - CHANGES: update. <Florent Kermarrec>
    * 5ddf350c - software/spisdcard: reduce SPISDCARD_CLK_FREQ to 16MHz. <Florent Kermarrec>
    * d6f92d1f - build: add DFUProg. <Florent Kermarrec>
    * 653edd17 - bios/boot: simplify flashboot (remove specific linux boot). <Florent Kermarrec>
    * 7b65a93c - bios/boot: add separators, update copyrights. <Florent Kermarrec>
    * f4abdd3f - bios/boot: make Ethernet boot mode flexible (now also using boot.json similarly to SDCard boot). <Florent Kermarrec>
    * c2ae22ee - bios/boot: make SDCard boot more flexible using a boot.json file on the SDCard. <Florent Kermarrec>
    * d918c0bb - software/bios/boot/sdcardboot: let FatFs do the SDCard initialization with disk_initialize. <Florent Kermarrec>
    * 51976008 - software/bios/boot: add sdcardboot support for VexRiscv SMP. <Florent Kermarrec>
    * 72026d44 - software/bios/main: clarify address space with @ instead of -. <Florent Kermarrec>
    * a01d08e5 - litex_setup.py: update microwatt. <Florent Kermarrec>
    *   a086237a - Merge pull request #564 from shenki/microwatt-updates <enjoy-digital>
    |\
    | * 748dcc1c - microwatt: Add mmu.vhdl <Joel Stanley>
    | * b57fc870 - microwatt: Update IRQ signal in wrapper <Joel Stanley>
    | * 68d2aa45 - microwatt: Add icache flush <Joel Stanley>
    | * e6909e29 - microwatt: Implement boot helper <Joel Stanley>
    * |   ace81c83 - Merge pull request #562 from gsomlo/gls-crlf <enjoy-digital>
    |\ \
    | * | 5575a921 - liblitesdcard: maintain unix newline convention across all source files <Gabriel Somlo>
    | |/
    * | 08bef5fc - software/liblitesdcard/ffconf: enable FF_FS_MINIMIZE and FF_FS_TINY. <Florent Kermarrec>
    * | 75225e5e - software/bios/boot: move f_mount to copy_image_from_sdcard_to_ram and force mount. <Florent Kermarrec>
    * | 59a048b6 - software/libliteeth/tftp: switch to progress bar. <Florent Kermarrec>
    * | f7e06a7e - bios/boot/copy_image_from_flash_to_ram: add missing init_progression_bar. <Florent Kermarrec>
    * | df9146fb - soc/spisdcard: use 32-bit SPIMaster and do 32-bit xfers in spisdcardreceive_block to optimize speed. <Florent Kermarrec>
    * | d45cfc1e - software/libbase/progress: avoid \t in progress bar, reduce HASHES_PER_LINE. <Florent Kermarrec>
    * | 5beba178 - software/libsdcard/spisdcard: add and use busy_wait_us to optimize speed. <Florent Kermarrec>
    * | dae15511 - bios/boot/copy_image_from_sdcard_to_ram: use chunks of 32KB to increase speed. <Florent Kermarrec>
    * | d294e0f1 - bios/boot: add progress bar to copy_image_from_flash_to_ram, use uint32_t in flash/sdcard functions. <Florent Kermarrec>
    * | 99f40fec - libase/progress: move __div64_32, do_div to div64.h/c as it was in Barebox. <Florent Kermarrec>
    * | 96fc96ec - software/liblitesdcard: remove read_block prototype, minor cleanup. <Florent Kermarrec>
    |/
    * fe9b42fa - bios/boot: use progress bar in copy_image_from_sdcard_to_ram. <Florent Kermarrec>
    * 21b9239d - libbase: add progress bar (from Barebox). <Florent Kermarrec>
    * 32ebbc77 - software/liblitesdcard: add retries when setting card to Idle. <Florent Kermarrec>
    * 04d0ba61 - software/liblitesdcard/sdcard: add FatFs disk functions. <Florent Kermarrec>
    * e27ed657 - software/liblitesdcard/spisdcard: rename #defines and allow external definition. <Florent Kermarrec>
    * a9e8860e - software/liblitesdcard: create fat directory for FatFs files. <Florent Kermarrec>
    * f1aba7e4 - sofware/liblitesdcard: enable Long Filename (LFN). <Florent Kermarrec>
    * fb282d1a - software/libsdcard: rewrite/simplify SPISDCard/FatFs support and only keep SDCard ver2.00+ compatibility. <Florent Kermarrec>
    *   20ff2462 - Merge pull request #559 from gsomlo/gls-fix-crlf <enjoy-digital>
    |\
    | * 78e3f251 - liblitesdcard: convert all sources to unix style newlines (cosmetic) <Gabriel Somlo>
    |/
    * c1806eba - software/liblitesdcard: remove unsused functions with FF_FS_READONLY. <Florent Kermarrec>
    * f9b43c81 - software/liblitesdcard: switch to FatFs for sdcardboot. <Florent Kermarrec>
    * f972c8e4 - software/liblitesdcard: base it on FatFs generic example code + LiteX's SPIMaster specific functions. <Florent Kermarrec>
    * 5b908983 - software/liblitesdcard: add FatFs files. <Florent Kermarrec>
    * 7d141258 - software/liblitesdcard/spisdcard: simplify/rewrite for consistency with the others parts of the project. - Improve code readability, remove un-needed or duplicate comments. - Only use a spi_xfer function for both write/read. - Set the SDCard to low clk freq before init and increase it when initialized. <Florent Kermarrec>
    * 860ac1e2 - software/liblitesdcard: add copyrights to spisdcard/fat16. <Florent Kermarrec>
    * 0ec50881 - software/liblitesdcard/sdcard: simplify readSector. <Florent Kermarrec>
    * 8c6f74d4 - software/liblitesdcard: fat16 boot working with both SPI and SD modes. <Florent Kermarrec>
    * bdaf6ff2 - software/liblitesdcard: move fat16 code to separate file to avoid duplication. <Florent Kermarrec>
    * 4b3c5203 - software/bios/libsdcard: add initial boot from sdcard with litescard, rename spisdcardboot command to sdcardboot. <Florent Kermarrec>
    * b30e3353 - soc/add_sdcard: use SDClockerS7 for 7-Series and SDClockerGen for others devices. <Florent Kermarrec>
    *   efbe1690 - Merge pull request #558 from antmicro/fix-function-names-liblitespi <enjoy-digital>
    |\
    | * eceee7e4 - litex/soc/software/liblitespi: fix names associated with PHY CSRs <Jan Kowalewski>
    |/
    * fb4b6c35 - boards/ulx3s: add sdcard pins and initial LiteSDCard integration. <Florent Kermarrec>
    * 997a17b9 - soc/add_sdcard: add minimal SDClockerECP5 on ECP5. <Florent Kermarrec>
    * 9a026c09 - soc/add_sdcard: remove limitation to 7-Series but only add clocker for it. <Florent Kermarrec>
    * c311f98c - soc/add_sdcard: emulator clocking moved to litesdcard. <Florent Kermarrec>
    * 382f239e - software/libsdcard: keep SDCARD_DEBUG enabled for now, fix typos. <Florent Kermarrec>
    * 20bbdaaf - soc/add_sdcard: remove Timer (unused). <Florent Kermarrec>
    * ab447df9 - software/liblitesdcard: review/simplify (code is over-complicated, revert part of the old code and write a minimal test for now). <Florent Kermarrec>
    * ee4056cf - software/liblitesdcard: remove sdtimer functions (unused). <Florent Kermarrec>
    *   ecfa44e5 - Merge pull request #556 from antmicro/mglb/symbiflow-fixes <enjoy-digital>
    |\
    | * 635a61e3 - targets/arty: use sys_clk_freq = 60MHz for Symbiflow toolchain <Mariusz Glebocki>
    | * 5071ef3e - build/xilinx/symbiflow: remap part name <Mariusz Glebocki>
    |/
    * 55723f13 - software/liblitedram: revert sdrsw() in sdrlevel: this is still required for sdrlevel command. <Florent Kermarrec>
    *   ddcf68c0 - Merge pull request #553 from ozbenh/sim-autoinit <enjoy-digital>
    |\
    | * 4a6256a5 - sdram: Unconditionally switch to SW control before inits <Benjamin Herrenschmidt>
    * |   47bb3d79 - Merge pull request #557 from antmicro/mor1kx_linux_booting <enjoy-digital>
    |\ \
    | * | f1e7d73e - bios: boot: Boot linux on mor1kx with external device tree and rootfs <Mateusz Holenko>
    * | | 10ff9d76 - CHANGES: update and change added features order. <Florent Kermarrec>
    |/ /
    * | 5d202ddb - test: update. <Florent Kermarrec>
    * | 01f7947b - targets: rename gateware-toolchain parameter to toolchain. <Florent Kermarrec>
    * | 245985d6 - targets/arty: integrate symbiflow changes to avoid duplication. <Florent Kermarrec>
    * | 89106873 - build/generic_platform: add default_clk constraints only when used. <Florent Kermarrec>
    * | 0cd613cc - build/xilinx/symbiflow: reuse .xdc generation from Vivado to avoid duplication, fix copyright. <Florent Kermarrec>
    * | 80ec5eca - boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform. <Florent Kermarrec>
    * | af928b26 - xilinx/simbiflow: add simple symbiflow_device re-mapping. <Florent Kermarrec>
    * |   5104d07a - Merge pull request #551 from antmicro/mglb/symbiflow-toolchain-xilinx-7-support <enjoy-digital>
    |\ \
    | * | 7434376c - test/test_targets: add arty_symbiflow <Mariusz Glebocki>
    | * | ae121aac - targets: add arty_symbiflow <Mariusz Glebocki>
    | * | 2bb2fbdb - platforms: add arty_symbiflow <Mariusz Glebocki>
    | * | bd702397 - build/xilinx: add Symbiflow toolchain support <Mariusz Glebocki>
    | |/
    * |   77139289 - Merge pull request #552 from ozbenh/memspeed-long <Tim Ansell>
    |\ \
    | * | 6239eac1 - sdram: Use unsigned long for memory test <Benjamin Herrenschmidt>
    | |/
    * |   a116578c - Merge pull request #550 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \
    | * | a433c837 - bios/litedram: add option to verify SPD EEPROM memory contents <Jędrzej Boczar>
    | * | 1692dfbf - build/sim/spdeeprom: use hex format when loading from file <Jędrzej Boczar>
    * | |   b98a9192 - Merge pull request #549 from antmicro/mglb/fix-vivado-yosys <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | a4e83234 - build/xilinx: do not assume build name is "top" <Mariusz Glebocki>
    |/ /
    * |   5cc7a988 - Merge pull request #547 from gsomlo/gls-fix-sdcard-status <enjoy-digital>
    |\ \
    | * | 28290efd - soc/software/litesdcard: update for response register back to 128 bits <Gabriel Somlo>
    * | | 395af900 - interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify. <Florent Kermarrec>
    * | | 511832a9 - soc/interconnect/axi: generate wishbone.sel for reads. <Florent Kermarrec>
    * | | 4f82a36a - soc/software: only keep 32-bit CSR alignment support. <Florent Kermarrec>
    |/ /
    * | 75936775 - wishbone/wishbone2csr: use wishbone.sel on CSR write. <Florent Kermarrec>
    * | b1ec092e - soc/software/litesdcard: use new send register to send command and remove CSR8_CMD_FIX. <Florent Kermarrec>
    * | efcba14b - platforms/nexys_video: add spisdcard pins. <Florent Kermarrec>
    * | 119ce56f - targets/nexys_video: add spi-sdcard and sdcard support. <Florent Kermarrec>
    * | cc595017 - plaforms/nexys_video: keep up to date with litex-boards. <Florent Kermarrec>
    * | 5cc564fb - targets: simplify Ethernet/Etherbone integration on targets with both. <Florent Kermarrec>
    * | 55c7461e - bios/cmds/cmd_litesdcard: rewrite comments/descriptions. <Florent Kermarrec>
    * | 6cb03963 - bios/main: replace / with -. <Florent Kermarrec>
    * |   5dd5f97b - Merge pull request #545 from gsomlo/gls-fix-mmptr <enjoy-digital>
    |\ \
    | * | 3e1b17d4 - csr: fix simple accessor alignment <Gabriel Somlo>
    * | | 6c1e2d84 - software/liblitesdcard: replace hexdump with dump_bytes already available in the BIOS. <Florent Kermarrec>
    |/ /
    * | 9e068a74 - soc/add_sdcard: add with_emulator parameter to use SDCard emulator (from Google Project Vault) and integrate it in litex_sim. <Florent Kermarrec>
    * | 2ae55e80 - setup.py: add litex_jtag_uart and litex_crossover_uart to console_scripts. <Florent Kermarrec>
    * | 62d939e8 - Merge pull request #543 from antmicro/jboc/eeprom-sim <enjoy-digital>
    |\|
    | * a0ce4ce5 - litex/build/sim: add module for simulating SPD EEPROM <Jędrzej Boczar>
    * | c4f96318 - targets/nexys4ddr: fix sdcard assert. <Florent Kermarrec>
    * | 76cc112e - bios: add main bus and csr bus infos, use KiB/GiB. <Florent Kermarrec>
    |/
    * 02072dea - integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically. <Florent Kermarrec>
    * 4b3afa75 - integration/soc: add add_sdcard method with integration code from nexys4ddr. <Florent Kermarrec>
    * c78caeb9 - csr: Fix definition(s) of CSR_BASE in generated headers <Benjamin Herrenschmidt>
    * f8bb500a - liblitedram/sdram: Add option to disable cdelay() <Benjamin Herrenschmidt>
    * 6d72ef28 - cpu/serv: add variants. <Florent Kermarrec>
    * fd7ec50e - soc/integration/export: add optional csr_base parameter. <Florent Kermarrec>
    * 795ff08a - build/sim/verilator: add regular_comb parameter (that defaults to False) and pass it to get_verilog. <Florent Kermarrec>
    *   25d2e7c9 - Merge pull request #542 from gsomlo/gls-sdcard-followup <enjoy-digital>
    |\
    | * 6da98ca1 - software/bios: fixup sdclk command <Gabriel Somlo>
    * |   3fd6ecd8 - Merge pull request #541 from antmicro/jboc/spd-read <enjoy-digital>
    |\ \
    | * | 1172c10a - bios: move I2C from liblitedram to libbase <Jędrzej Boczar>
    | * | 472bf9ac - bios/sdram: expose I2C functions <Jędrzej Boczar>
    | * | bdc7eb5c - litex_sim: load SPD data from files in hexdump format as printed in BIOS <Jędrzej Boczar>
    | * | a42dc974 - bios/sdram: add BIOS command for reading SPD <Jędrzej Boczar>
    | * | 8fd3e74e - bios/sdram: add firmware for reading SPD EEPROM <Jędrzej Boczar>
    * | | 68f83cbc - CHANGES: document deprecated/moved modules. <Florent Kermarrec>
    * | | ab806060 - soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone. <Florent Kermarrec>
    * | | 0a3d649a - interconnect/wishbone: integrate Wishbone2CSR. <Florent Kermarrec>
    * | | b5b88d27 - interconnect/csr_bus: add separators. <Florent Kermarrec>
    * | | 86952a6e - interconnect/wishbone: remove CSRBank (probably not used by anyone). <Florent Kermarrec>
    * | | e404608c - interconnect/wishbone: add separators and move SDRAM/Cache. <Florent Kermarrec>
    * | | 1fddd0e3 - interconnect/wishbone: simplify DownConverter. <Florent Kermarrec>
    * | | e0d26820 - interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten). <Florent Kermarrec>
    | |/
    |/|
    * | 696b31ed - tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM. <Florent Kermarrec>
    * | 2efcf879 - targets/nexys4ddr: update add_sdcard method. <Florent Kermarrec>
    * | 2934c085 - CHANGES: add JTAG UART. <Florent Kermarrec>
    * | 3b47d4a4 - tools/litex_jtag_uart: add openocd config and telnet port parameters. <Florent Kermarrec>
    * | 67cf6703 - cpus: remove common cpu variants/extensions definition and simplify variant check. <Florent Kermarrec>
    * | 062ff67e - cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin. <Florent Kermarrec>
    * | 24687cbd - tools/litex_client/RemoteClient: add base_address parameter. <Florent Kermarrec>
    * | 78a9579e - cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word. <Florent Kermarrec>
    * |   370e4652 - Merge pull request #539 from dayjaby/pr-fix_uart_startbit <enjoy-digital>
    |\ \
    | * | e853ad4b - fix uart startbit: 1 cycle later <David Jablonski>
    * | | c75cf45a - tools: add litex_jtag_uart to create a virtual uart for the jtag uart. <Florent Kermarrec>
    * | | 2cf83b9f - tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now. <Florent Kermarrec>
    * | | bed5aafd - tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...). <Florent Kermarrec>
    * | | 3833bc3e - litex_sim: override uart_name to sim only for serial. <Florent Kermarrec>
    * | | da7fd308 - CHANGES: update. <Florent Kermarrec>
    * | | 2fb52e66 - integration/soc: remove TODO in header. <Florent Kermarrec>
    * | | b65f18c3 - cpu/cv32e40p: fix copyright year. <Florent Kermarrec>
    * | | 30f35170 - cpu/cv32e40p: add copyright and improve indentation. <Florent Kermarrec>
    * | | b23702ec - litex_setup/pythondata-cpu-cv32e40p: clone in recursive mode. <Florent Kermarrec>
    * | |   4c4cd335 - Merge pull request #535 from antmicro/arty-cv32e40p <enjoy-digital>
    |\ \ \
    | * | | 2d6ee5aa - cores/cpu: add cv32e40p <Piotr Binkowski>
    | * | | ca8cb834 - software/bios/isr: add support for cv32e40p <Piotr Binkowski>
    | * | | 2903b1bf - litex_setup: add pythondata for cv32e40p <Piotr Binkowski>
    * | | |   7d09ea19 - Merge pull request #538 from antmicro/fix_libbase <enjoy-digital>
    |\ \ \ \
    | * | | | 9d16b0fc - libbase: Include missing uart header <Mateusz Hołenko>
    |/ / / /
    * | | | 3d06dc02 - test/test_targets: update build_test. <Florent Kermarrec>
    * | | | 42350f6d - platforms/targets: keep in sync with litex-boards. <Florent Kermarrec>
    * | | | 2eea7864 - build/sim: rename dut to sim (for consistency with other builds). <Florent Kermarrec>
    * | | | a6cbbc9d - integration/soc: set build_name to platform.name when not specified. <Florent Kermarrec>
    * | | | 16417cb8 - software/liblitespi: fix #endif location. <Florent Kermarrec>
    * | | |   9bdb063b - Merge pull request #516 from antmicro/i2s_support_arty <enjoy-digital>
    |\ \ \ \
    | * | | | ce499900 - Extend I2S capabilities <Pawel Sagan>
    * | | | |   c2e9a26e - Merge pull request #534 from fjullien/fix_litex_sim_warn <enjoy-digital>
    |\ \ \ \ \
    | |/ / / /
    |/| | | |
    | * | | | 7c5f56c2 - litex/sim: fix compiler warnings <Franck Jullien>
    |/ / / /
    * | | |   6fedaa70 - Merge pull request #533 from antmicro/fix-dummy-bits-function-name <enjoy-digital>
    |\ \ \ \
    | * | | | ab41e27e - software/liblitespi/spiflash: fix dummy bits setup function name <Jan Kowalewski>
    |/ / / /
    * | | | d71152ef - litex_setup: move requests import to avoid having to install it on travis. <Florent Kermarrec>
    * | | | 9854fdd5 - .travis: install  requests package before running litex_setup.py. <Florent Kermarrec>
    * | | | bd0f21ba - targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets). <Florent Kermarrec>
    * | | | 80eca300 - software/liblitespi/spiflash: review/simplify/update and test on arty. <Florent Kermarrec>
    * | | | 4a175620 - build/xilinx: simplify LITEX_ENV_ISE/VIVADO handling. <Florent Kermarrec>
    * | | | e91c3171 - software/bios: cleanup includes and specify the lib in the include. <Florent Kermarrec>
    * | | | c3a03d0d - software: create liblitespi and mode litespi code to it (with some parts commented out for now). <Florent Kermarrec>
    * | | | 61238bee - soc/software/bios: add autoconfiguration functionality for LiteSPI core <Jan Kowalewski>
    * | | | d3890055 - litex_setup: add automatic update of litex_setup (because it also changes) and be sure we are on master branch before update. <Florent Kermarrec>
    * | | |   939f546a - Merge pull request #531 from gsomlo/gls-bios-linker <enjoy-digital>
    |\ \ \ \
    | |_|/ /
    |/| | |
    | * | | c5524dbf - software/bios: fix link order to avoid undefined symbol errors <Gabriel Somlo>
    |/ / /
    * | | b4267a79 - build/xilinx: source settings64.sh automatically just before build if LITEX_ENV_ISE/LITEX_ENV_VIVADO environment variables are set. <Florent Kermarrec>
    * | | de7e0ee9 - integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed. <Florent Kermarrec>
    * | | 6f8f0d23 - litex_setup: add litehyperbus and remove hyperbus core/test. <Florent Kermarrec>
    |/ /
    * | 109fd267 - integration/builder: simplify default output_dir to "build/platform". <Florent Kermarrec>
    * | 55c0ddab - litex_setup: add sha1 support on git clone/pull and fix microwatt to a specific sha1. <Florent Kermarrec>
    |/
    *   23d43a2c - Merge pull request #530 from enjoy-digital/bios-libs <enjoy-digital>
    |\
    | * 7192397a - software/libbase: remove linker-sdram (unused). <Florent Kermarrec>
    | * b4b84def - software/bios: mode spisdcard code to liblitesdcard. <Florent Kermarrec>
    | * 21e2a34c - software/bios: rename commands to cmds and update with libs' names. <Florent Kermarrec>
    | * 33f6ce74 - software/bios: move hw flags definitions to respective libs, remove hw/flags.h. <Florent Kermarrec>
    | * 403355a8 - software: create liblitescard and move sdcard init/test code to it. <Florent Kermarrec>
    | * 920d0ee5 - software: create liblitedram and move sdram init/test code to it. <Florent Kermarrec>
    | * c95084e5 - bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash. <Florent Kermarrec>
    | * 573a8815 - software/bios/commands: rename cmd_mdio to cmd_liteeth. <Florent Kermarrec>
    | * ff8d9e61 - software/bios: move mdio to libliteeth. <Florent Kermarrec>
    | * 70a67ce7 - software/bios: rename libnet to libliteeth and move all ethernet files to it. <Florent Kermarrec>
    | * 56b8723b - software/bios: rename cmd_mem_access to cmd_mem. <Florent Kermarrec>
    |/
    * a02077d5 - cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build. <Florent Kermarrec>
    * b5352f40 - cpu/microwatt: update microwatt_wraper.vhdl <Florent Kermarrec>
    * be25500e - uptime: rework and integrate it in Timer to ease software support. <Florent Kermarrec>
    * d6549ff8 - bios: add uptime command and rewrite cmd_bios comments. <Florent Kermarrec>
    * fc0e55be - soc: improve uptime comments. <Florent Kermarrec>
    *   840679ad - Merge pull request #526 from rprinz08/master <enjoy-digital>
    |\
    | * 3f649077 - Make booting from SD-Card to behave same as from SPI flash <rprinz08>
    * | 82364de5 - soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled. <Florent Kermarrec>
    |/
    * 3391398a - bios/sdram: always show bitslip on two digits to keep scan aligned. <Florent Kermarrec>
    *   4a5072a0 - Merge pull request #517 from ozbenh/csr-access-rework <enjoy-digital>
    |\
    | * 1e35b0e7 - csr: Rework accessors <Benjamin Herrenschmidt>
    |/
    * d4f44597 - CHANGES: update. <Florent Kermarrec>
    *   a51c7a7b - Merge pull request #518 from enjoy-digital/csr_base <enjoy-digital>
    |\
    | * 748ef1ad - export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses. <Florent Kermarrec>
    * |   177c1e53 - Merge pull request #523 from DurandA/patch-5 <enjoy-digital>
    |\ \
    | * | 9d9e7d54 - Update litex_term help <Arnaud Durand>
    |/ /
    * | 2e59dc32 - platforms/nexys4ddr: add card detect pin to sdcard. <Florent Kermarrec>
    * | 51742be2 - integration/soc: review/simplify interconnect and add logger.info. <Florent Kermarrec>
    * |   78413cc0 - Merge pull request #519 from ozbenh/point2point <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 1ed68691 - soc: Revive generation of a PointToPoint interconnect <Benjamin Herrenschmidt>
    |/
    * 9f941138 - test/test_targets: workaround to fix travis. <Florent Kermarrec>
    * 9d1443c1 - cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that. <Florent Kermarrec>
    * 5ea3bae0 - bios/boot: review/fix #503. <Florent Kermarrec>
    *   bf7857f5 - Merge pull request #503 from rprinz08/master <enjoy-digital>
    |\
    | * 1f55fcf4 - fixed bug in BIOS spi flash "fw" command <rprinz08>
    | * f062c0c4 - removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram <rprinz08>
    | * ea232fc5 - BIOS boot firmware from SPI with address offset <rprinz08>
    * |   b4e349eb - Merge pull request #513 from mubes/bios_linker <enjoy-digital>
    |\ \
    | * | d2d82dac - Bios linker edits to prevent inappropriate optimisation <Dave Marples>
    |/ /
    * | 3fb99b7d - cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite. <Florent Kermarrec>
    * |   2a5a7536 - Merge pull request #478 from antmicro/extended_spi_flash <enjoy-digital>
    |\ \
    | * | 00f973ea - spi_flash: extend non-bitbanged flash support <Jakub Cebulski>
    | * | a344e20b - spi_flash: fix building without bitbang <Jakub Cebulski>
    * | |   7d79da8e - Merge pull request #510 from mubes/colorlight_usb <enjoy-digital>
    |\ \ \
    | * | | 84997332 - Fix dumb missing line <Dave Marples>
    | * | |   33e202ed - Bring into line with master <Dave Marples>
    | |\ \ \
    | * | | | dc1d4520 - Addition of boot address parameter for trellis builds <Dave Marples>
    * | | | | 3a6dd95d - integration/soc: review/simplify changes for standalone cores. <Florent Kermarrec>
    * | | | |   0d5eb133 - Merge pull request #511 from ozbenh/standalone-cores <enjoy-digital>
    |\ \ \ \ \
    | * | | | | f628ff6b - WB2CSR: Use CSR address_width for the wishbone bus <Benjamin Herrenschmidt>
    | * | | | | 520c17e9 - soc_core: Add option to override CSR base <Benjamin Herrenschmidt>
    | * | | | | ecbd4028 - soc: Don't update CSR alignment when there is no CPU <Benjamin Herrenschmidt>
    | * | | | | f28f2471 - soc: Don't create a wishbone slave to LiteDRAM with no CPU <Benjamin Herrenschmidt>
    | * | | | | dcc881db - soc: Don't create a share intercon with only one master and one slave <Benjamin Herrenschmidt>
    | | |/ / /
    | |/| | |
    * | | | | 873d95e5 - interconnect/wishbonebridge: refresh/simplify. <Florent Kermarrec>
    * | | | |   c136113a - Merge pull request #506 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \ \ \
    | * | | | | aed1d514 - Update README.md and core.py for BlackParrot <sadullah>
    | * | | | | 5e4a4360 - Vivado Command Update for Systemverilog <sadullah>
    | |/ / / /
    * | | | |   d2c9d385 - Merge pull request #508 from antmicro/update_litesdcard <enjoy-digital>
    |\ \ \ \ \
    | |/ / / /
    |/| | | |
    | * | | | 0db35069 - Update Litex bios to handle updated litesdcard. <Kamil Rakoczy>
    |/ / / /
    * | | |   3ce90100 - Merge pull request #505 from DurandA/patch-3 <enjoy-digital>
    |\ \ \ \
    | * | | | 2c40967b - Enable 1x mode on SPI flash <Arnaud Durand>
    | | |_|/
    | |/| |
    * | | | e2176cef - soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters. <Florent Kermarrec>
    * | | | 1e610600 - build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends. <Florent Kermarrec>
    * | | |   ebcf67c1 - Merge pull request #502 from shuffle2/master <enjoy-digital>
    |\ \ \ \
    | * | | | eeee179d - diamond: close project when done <Shawn Hoffman>
    | * | | | 9b782bd7 - diamond: clock constraint improvements <Shawn Hoffman>
    | |/ / /
    * | | |   80f5327e - Merge pull request #490 from daveshah1/rdimm_bside_init <enjoy-digital>
    |\ \ \ \
    | * \ \ \   13db89eb - Merge branch 'master' into rdimm_bside_init <enjoy-digital>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | c9e36d7f - lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args. <Florent Kermarrec>
    * | | | | ea7fe383 - lattice/trellis: simplify seed support and add it to trellis_args. <Florent Kermarrec>
    * | | | |   5ee01c94 - Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed <enjoy-digital>
    |\ \ \ \ \
    | * | | | | ac1e9683 - Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs` <Ilya Epifanov>
    * | | | | |   5987ddb4 - Merge pull request #485 from ilya-epifanov/cpu-imac-config-for-vexriscv <enjoy-digital>
    |\ \ \ \ \ \
    | * \ \ \ \ \   c5f74a5a - Merge branch 'master' into cpu-imac-config-for-vexriscv <enjoy-digital>
    | |\ \ \ \ \ \
    | |/ / / / / /
    |/| | | | | |
    * | | | | | | 59d88a88 - integration/soc/add_adapter: rename is_master to direction. <Florent Kermarrec>
    * | | | | | |   57390666 - Merge pull request #504 from sergachev/master <enjoy-digital>
    |\ \ \ \ \ \ \
    | * | | | | | | e4fa4bbc - integration/soc: fix add_adapter for slaves <Ilia Sergachev>
    |/ / / / / / /
    * | | | / / / 2d70220b - bios: Fix warning on 64-bit <Benjamin Herrenschmidt>
    | |_|_|/ / /
    |/| | | | |
    * | | | | | fbbbdf03 - core/led: simplify LedChaser (to have the same user interface than GPIOOut). <Florent Kermarrec>
    * | | | | | 05869beb - cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :)) <Florent Kermarrec>
    * | | | | | 90c485fc - integration/soc: add clock_domain parameter to add_etherbone. <Florent Kermarrec>
    * | | | | | f1a50a21 - integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge). <Florent Kermarrec>
    | |_|_|/ /
    |/| | | |
    * | | | | 79ee135f - bios/sdram: fix lfsr typo. <Florent Kermarrec>
    * | | | |   162d3260 - Merge pull request #500 from mubes/fixups <enjoy-digital>
    |\ \ \ \ \
    | * \ \ \ \   2a37b97d - Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups <Dave Marples>
    | |\ \ \ \ \
    | * | | | | | 967e38bb - Small fixups to address compiler warnings etc. <Dave Marples>
    | | |_|_|_|/
    | |/| | | |
    * | | | | | d74f8fc9 - build/xilinx: add disable_constraints parameter to Platform.add_ip. <Florent Kermarrec>
    | |/ / / /
    |/| | | |
    * | | | | 84841e1d - bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt). <Florent Kermarrec>
    * | | | | 99c5b0fc - bios/sdram: Use an LFSR to speed up pseudo-random number generation <Benjamin Herrenschmidt>
    * | | | |   34f26868 - Merge pull request #499 from DurandA/patch-2 <enjoy-digital>
    |\ \ \ \ \
    | * | | | | 5e049d89 - Add data dirs to manifest <Arnaud Durand>
    * | | | | | 8b9aa16d - boards/platforms: update xilinx programmers. <Florent Kermarrec>
    * | | | | | 3c34039b - build/xilinx/vivado: ensure Vivado process our .xdc early. <Florent Kermarrec>
    |/ / / / /
    * | | | | b0578580 - gen/fhdl/verilog: explicitly define input/output/inout wires. <Florent Kermarrec>
    * | | | | 0aa3c339 - targets/genesys2: set cmd_latency to 1. <Florent Kermarrec>
    * | | | | 95b57899 - bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases). <Florent Kermarrec>
    * | | | | 98d1b451 - platforms/targets: fix CI. <Florent Kermarrec>
    * | | | | 22bcbec0 - boards: keep in sync with LiteX-Boards, integrate improvements. <Florent Kermarrec>
    * | | | | 28f85c74 - build/lattice/programmer: add UJProg (for ULX3S). <Florent Kermarrec>
    * | | | | 85ac5ef1 - build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer. <Florent Kermarrec>
    * | | | | 9a7f9cb8 - build/generic_programmer: catch 404 not found when downloading config/proxy. <Florent Kermarrec>
    * | | | | d0b8daa0 - build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request. <Florent Kermarrec>
    * | | | | b8f9f83a - build/openocd: add find_config method to allow using local config file or download it if not available locally. <Florent Kermarrec>
    * | | | | 9bef218a - cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt). <Florent Kermarrec>
    * | | | |   6f24d46d - Merge pull request #496 from gsomlo/gls-fix-makefiles <enjoy-digital>
    |\ \ \ \ \
    | * | | | | edfed4f0 - software/*/Makefile: no need to copy .S files from CPU directory <Gabriel Somlo>
    |/ / / / /
    * | | | |   7f8e34c6 - Merge pull request #494 from shuffle2/patch-2 <enjoy-digital>
    |\ \ \ \ \
    | * | | | | ee413527 - diamond: quiet warning about missing clkin freq for EHXPLLL <shuffle2>
    |/ / / / /
    * | | | | 07e0153b - CHANGES: update. <Florent Kermarrec>
    * | | | | 21127031 - cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple. <Florent Kermarrec>
    * | | | | c06a1279 - cpu/microwatt: add pythondata and fix build with it. <Florent Kermarrec>
    * | | | | 45377d9f - cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width. <Florent Kermarrec>
    * | | | | 7c69a6db - bios/cmd_mdio.c:  fix missing <base/mdio.h> import. <Florent Kermarrec>
    * | | | | b0205335 - cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c. <Florent Kermarrec>
    * | | | | 97e534d0 - cpus: add nop instruction and use it to simplify the BIOS. <Florent Kermarrec>
    * | | | | 4efc7835 - cpus: add human_name attribute and use it to simplify the BIOS. <Florent Kermarrec>
    * | | | | d81f171c - software/libbase/system.c: remove unused includes. <Florent Kermarrec>
    * | | | |   3bbadb35 - Merge pull request #492 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \ \ \
    | * \ \ \ \   999b93af - Merge branch 'master' into blackparrot_litex <enjoy-digital>
    | |\ \ \ \ \
    | |/ / / / /
    |/| | | | |
    * | | | | |   705d3887 - Merge pull request #474 from fjullien/term_hist_auto_compl <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | 74dc444b - bios: add auto completion for commands <Franck Jullien>
    | * | | | | | fc2b8226 - bios: switch command handler to a modular format <Franck Jullien>
    | * | | | | | 86cab3d3 - bios: move helper functions to their own file <Franck Jullien>
    | * | | | | | bc5a1986 - bios: add terminal history <Franck Jullien>
    | * | | | | | e764eabd - builder: add a parameter to pass options to BIOS Makefile <Franck Jullien>
    | | * | | | | 0c770e06 - Update README.md <Sadullah Canakci>
    | | * | | | | 19bb1b9b - update to comply with python-data layout <sadullah>
    | | * | | | | 3eb9efd6 - BP fpga recent version <sadullah>
    | | * | | | | bf864d33 - Fix memory transducer bug, --with-sdram for BIOS works, memspeed works <sadullah>
    | | * | | | | cf01ea65 - rebased, minor changes in core.py <sadullah>
    | | * | | | | b7b9a1f0 - Linux works, LiteDRAM works (need cleaning, temporary push) <sadullah>
    | | * | | | | 74140587 - Create GETTING STARTED <Sadullah Canakci>
    | |/ / / / /
    |/| | | | |
    * | | | | |   e853cac6 - Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | a11f1c39 - Removed erase flag and made progress output less noisy <Ilya Epifanov>
    | | |_|_|/ /
    | |/| | | |
    * | | | | |   a6779b9d - Merge pull request #491 from gsomlo/gls-spisd-clusters <enjoy-digital>
    |\ \ \ \ \ \
    | * | | | | | c8e3bba4 - software: spisdcard: cosmetic: avoid filling screen with cluster numbers <Gabriel Somlo>
    * | | | | | | b5978b21 - .travis.yml: disable python3.5 test (nMigen requires 3.6+). <Florent Kermarrec>
    * | | | | | | 10371a33 - CHANGES: update. <Florent Kermarrec>
    * | | | | | | bd8a4100 - cpu/minerva: add pythondata and use it to compile the sources. <Florent Kermarrec>
    * | | | | | | e4a4659d - litex_setup: add nmigen dependency (used to generate Minerva CPU). <Florent Kermarrec>
    * | | | | | | d3e3ca06 - CHANGES: start listing changes for next release. <Florent Kermarrec>
    |/ / / / / /
    * | / / / / 3c70c83f - cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs. <Florent Kermarrec>
    | |/ / / /
    |/| | | |
    * | | | | bb70a232 - cpu/software: move CPU specific software from the BIOS to the CPU directories. <Florent Kermarrec>
    * | | | | 0abc7d4f - cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository. <Florent Kermarrec>
    * | | | | b82b3b7e - integration/soc: rename usb_cdc to usb_acm. <Florent Kermarrec>
    * | | | | 0a1afbf6 - litex/__init__.py: remove retro-compat > 6 months old. <Florent Kermarrec>
    * | | | | 3531a641 - soc: allow passing custom CPU class to SoC. <Florent Kermarrec>
    | | | * | 83f4dcb2 - Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv <Ilya Epifanov>
    | | |/ /
    | |/| |
    | | | * 64b50515 - Add RDIMM side-B inversion support <David Shah>
    | |_|/
    |/| |
    * | |   90a6343d - Merge pull request #488 from enjoy-digital/python3.5 <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 9941e4c1 - travis: add back test on python3.5 (python3.6 is recommended but we can try to keep 3.5 compatibility until we have good reason to no longer support it). <Florent Kermarrec>
    |/ /
    * |   855d614e - Merge pull request #481 from betrusted-io/unfstringify <enjoy-digital>
    |\ \
    | * | 17b76654 - propose patch to not break litex for python 3.5 <bunnie>
    |/ /
    * | 56aa7897 - create first release, add CHANGES and note about Python modules in README. <Florent Kermarrec>
    * | 6d0896de - cpu/serv: switch to pythondata package instead of local git clone. <Florent Kermarrec>
    * | 1b069268 - README: update Python minimal version to 3.6. <Florent Kermarrec>
    * | ff61b1f6 - litex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX data. <Florent Kermarrec>
    * |   4d86ab9d - Merge pull request #399 from mithro/litex-sm2py <enjoy-digital>
    |\ \
    | * \   317ea7ed - Merge branch 'master' into litex-sm2py <enjoy-digital>
    | |\ \
    | * | | 1f356695 - litex_sim: Find tapcfg from pythondata module. <Tim 'mithro' Ansell>
    | * | | 3aee8a52 - Remove directories from submodules from MANIFEST.in file. <Tim 'mithro' Ansell>
    | * | | ebcb2a44 - Rename litex-data-XXX-YYY to pythondata-XXX-YYY <Tim 'mithro' Ansell>
    | * | | a39a4ec2 - Only allow fast-forward pulls. <Tim 'mithro' Ansell>
    | * | | e618d41f - Fixing mor1kx data finding. <Tim 'mithro' Ansell>
    | * | | 2e3b7f20 - Fix typo in error message. <Tim 'mithro' Ansell>
    | * | | 83b25813 - Fix the libcompiler_rt path. <Tim 'mithro' Ansell>
    | * | | 1c1c5bcb - Remove submodules. <Tim 'mithro' Ansell>
    | * | | c96d1e66 - Fix import for data. <Tim 'mithro' Ansell>
    | * | | 119985f3 - Use the current directory you are running. <Tim 'mithro' Ansell>
    | * | | 69367f8d - Make litex a namespace. <Tim 'mithro' Ansell>
    | * | | 3ae4f8f2 - Adding missing vexriscv CPU. <Tim 'mithro' Ansell>
    | * | | ac3fd794 - Adding missing comma. <Tim 'mithro' Ansell>
    | * | | 3df6c0c8 - Adding litex-data-software-compiler_rt as a required package. <Tim 'mithro' Ansell>
    | * | | 3964565e - Fixed quotes in `litex_setup.py` <Tim 'mithro' Ansell>
    | * | | d5a21a75 - Converting litex to use Python modules. <Tim 'mithro' Ansell>
    |  / /
    * | | 5ef869b9 - soc/cpu: add memory_buses to cpus and use them in add_sdram. <Florent Kermarrec>
    * | | 467fee3e - soc/cpu: rename cpu.buses to cpu.periph_buses. <Florent Kermarrec>
    |/ /
    * |   05815c4e - Merge pull request #477 from shuffle2/patch-1 <enjoy-digital>
    |\ \
    | * | f71014b9 - diamond: fix include paths <shuffle2>
    |/ /
    * | 4dece4ce - soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). <Florent Kermarrec>
    * |   c5ef9c73 - Merge pull request #473 from fjullien/memusage <enjoy-digital>
    |\ \
    | * | 3892d7a9 - bios: print memory usage <Franck Jullien>
    * | | 9460e048 - tools/litex_sim: use similar analyzer configuration than wiki. <Florent Kermarrec>
    * | |   443cc72d - Merge pull request #476 from enjoy-digital/serv <enjoy-digital>
    |\ \ \
    | * | | 1d1a4ecd - software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning. <Florent Kermarrec>
    | * | | fb9e369a - serv: connect reset. <Florent Kermarrec>
    | * | | 71778ad2 - serv: update copyrights (Greg Davill found the typos/issues). <Florent Kermarrec>
    | * | | 1f9db583 - serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :). <Florent Kermarrec>
    | * | | 2efd939d - serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill). <Florent Kermarrec>
    | * | | 22c39236 - initial SERV integration. <Florent Kermarrec>
    | | |/
    | |/|
    * | | c4c891de - build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis). <Florent Kermarrec>
    * | |   192849f0 - Merge pull request #475 from gregdavill/read_verilog_defer <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | 642c4b30 - build/trellis: add verilog_read -defer option to yosys script <Greg Davill>
    |/ /
    * | 96e7e6e8 - bios/sdram: reduce number of scan loops during cdly scan to speed it up. <Florent Kermarrec>
    * | 43e1a5d6 - targets/kcu105: use cmd_latency=1. <Florent Kermarrec>
    * | 85a059bf - bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal. <Florent Kermarrec>
    * | 038e1bc0 - targets/kc705: manual DDRPHY_CMD_DELAY no longer needed. <Florent Kermarrec>
    * | aaed4b94 - bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle. <Florent Kermarrec>
    * |   33c7b2ce - Merge pull request #472 from antmicro/jboc/sdram-calibration <enjoy-digital>
    |\ \
    | * | ab92e81e - bios/sdram: add automatic cdly calibration during write leveling <Jędrzej Boczar>
    * | |   4608bd18 - Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | b0f8ee98 - litex_sim: add option to create SDRAM module from SPD data <Jędrzej Boczar>
    * | | 0b3c4b50 - soc/cores/spi: add optional aligned mode. <Florent Kermarrec>
    * | | 6bb22dfe - cores/spi: simplify. <Florent Kermarrec>
    * | | fc434af9 - build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt). <Florent Kermarrec>
    * | | 1457c320 - xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale. <Florent Kermarrec>
    * | | 69462e66 - build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input. <Florent Kermarrec>
    * | | 65e6ddc6 - lattice/common: add LatticeECP5DDRInput. <Florent Kermarrec>
    * | | 2031f280 - lattice/common: cleanup instances, simplify tritates. <Florent Kermarrec>
    * | | 2d25bcb0 - lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput. <Florent Kermarrec>
    | |/
    |/|
    * | 56e15284 - platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. <Florent Kermarrec>
    * | 08e4dc02 - tools/remote/etherbone: update import. <Florent Kermarrec>
    |/
    * 19f983c4 - targets: manual define of the SDRAM PHY no longer needed. <Florent Kermarrec>
    * c0f3710d - bios/sdram: update/simplify with new exported LiteDRAM parameters. <Florent Kermarrec>
    * 3915ed97 - litex_sim: add phytype to PhySettings. <Florent Kermarrec>
    * c0c5ae55 - build/generic_programmer: move requests import to do it only when needed. <Florent Kermarrec>
    * c9ab5939 - bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4. <Florent Kermarrec>

 * litex-boards changed from cb95962 to 1356ebb
    * 1356ebb - targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset. <Florent Kermarrec>
    *   4997399 - Merge pull request #85 from oskirby/logicbone <enjoy-digital>
    |\
    | * 76a32ba - Add Logicbone ECP5 board <Owen Kirby>
    * | efe33c9 - targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3). <Florent Kermarrec>
    * | 6753a92 - targets: add fixed sdcard clock on boards with SDCard support. <Florent Kermarrec>
    * | 782c856 - platforms/genesys2: add usb_fifo. <Florent Kermarrec>
    * | 936ba5b - platforms/genesys2: add openocd specific …
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@mithro @cr1901