Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

qemu complier flags changed, #include <> needs to be "" #49

Closed
CarlFK opened this issue Sep 5, 2018 · 15 comments
Closed

qemu complier flags changed, #include <> needs to be "" #49

CarlFK opened this issue Sep 5, 2018 · 15 comments
Labels

Comments

@CarlFK
Copy link
Contributor

CarlFK commented Sep 5, 2018

I don't know what repo this code comes from, but here is the change:

(LX P=arty C=or1k) juser@cnt6:~/litex-buildenv/third_party/litex$ git diff
diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py
index bc934cf3..dfea77e3 100644
--- a/litex/soc/integration/cpu_interface.py
+++ b/litex/soc/integration/cpu_interface.py
@@ -136,7 +136,7 @@ def _get_rw_functions_c(reg_name, reg_base, nwords, busword, read_only, with_acc
 def get_csr_header(regions, constants, with_access_functions=True, with_shadow_base=True, shadow_base=0x80000000):
     r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n"
     if with_access_functions:
-        r += "#include <hw/common.h>\n"
+        r += '#include "hw/common.h"\n'
     for name, origin, busword, obj in regions:
         if not with_shadow_base:
             origin &= (~shadow_base)
@mithro
Copy link
Member

mithro commented Sep 5, 2018

We can't really change this here as it'll break other firmware...

@mithro
Copy link
Member

mithro commented Sep 5, 2018

I think we need to change the ./scripts/build-qemu.sh script to add an extra include path to CFLAGS?

@CarlFK
Copy link
Contributor Author

CarlFK commented Sep 5, 2018 via email

@mithro
Copy link
Member

mithro commented Sep 5, 2018

Look forward to the pull request!

@stffrdhrn
Copy link
Contributor

For short term this sounds fine.

I think in the long run when upstreaming the qemu patches we need to provide some defaults in qemu for generated/csr.h and generated/mem.h. Then, when building in latex environment, we can inject CFLAGS to override the qemu provided csr.h / mem.h files.

@ewenmcneill
Copy link
Contributor

@stffrdhrn @mithro FWIW, I've been thinking that we probably need to do the same thing (with the same files) in the MicroPython port (ports/fupy) as well, so possibly we want to agree on a standard default layout for holding a cached version of generated files. I'm assuming they're at least board specific, and maybe soft CPU/variant specific as well?

In which case possibly we want a target/$(BOARDNAME)/generated directory for each board to hold generated defaults, plus a way of injecting an -I in "development mode" before that include directory is reached for the case of building in the litex-buildenv environment where the most recently generated ones for the desired target can be used. Plus maybe a default for the BOARDNAME for building in just the qemu tree (or perhaps a "make BOARDNAME" type set of options that sets BOARDNAME appropriately for those includes, and does a recursive make).

If y'all come up with something clean/flexible to do that for qemu I'm happy to replicate it in our MicroPython port as well (inside ports/fupy).

Ewen

@stffrdhrn
Copy link
Contributor

stffrdhrn commented Sep 8, 2018

@ewenmcneill one thought I have is for qemu to support device tree. This will allow the memory locations and device layout to be determined at boot/runtime instead of compiled into the binary. There is some discussion on this here: https://elinux.org/CELF_Project_Proposal/Add_Device_Tree_emulation_support_to_QEMU. This is now fully supported in qemu with the qemu_fdt_* apis, see examples in hw/microblaze/boot.c (microblaze_load_dtb())? Do you think MicroPython would want/use something like that?

Also, I remember @mithro mentioning that he was updating litex to generate devicetrees for the linux kernel during litex build. I am not sure how far that has gotten.

@stffrdhrn
Copy link
Contributor

stffrdhrn commented Sep 8, 2018

@ewenmcneill oh... it looks like its already being discussed here: https://github.com/timvideos/litex-buildenv/wiki/DeviceTree

If we agree I will go about converting the litex hardware in qemu to device tree.

GitHub
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! - timvideos/litex-buildenv

@mithro
Copy link
Member

mithro commented Sep 9, 2018

There is code here -> https://github.com/mithro/litex-devicetree

I thought upstream QEMu rejected the idea of using DeviceTree for configuration?

GitHub
Tool for generating Linux compatible DeviceTree from a LiteX csr.csv definition. - mithro/litex-devicetree

@ewenmcneill
Copy link
Contributor

@stffrdhrn If upstream Qemu will agree to DeviceTree for configuration (at least for this particular varient -- litex) then I think that's probably the ideal medium term goal. We talked about it (at PyConAU 2018) with the upstream MicroPython developers and there was some interest in using DeviceTree for the ports/fupy (litex) port of MicroPython too.

Given what @mithro says, it'd probably make sense to confirm that upstream Qemu will accept DeviceTree (or definitely includes it already) -- that discussion you linked to seemed somewhat inconclusive whether it'd be accepted. If they will I'm happy to encourage our MicroPython port in that direction too (and it might well go that way even if Qemu doesn't).

Ewen

@stffrdhrn
Copy link
Contributor

@ewenmcneill , @mithro I have been asking about device tree in #qemu but it seems no one is online yet. But I was looking and thinking. It seems that the qemu support for device tree is mostly around reading device tree which is to be passed to the kernel. Qemu can inject / override things to pass on to the kernel. That would work fine for the kernel, but it doesn't work for software that doesn't understand device tree.

Maybe the idea is to add device tree support to the litex bios / micropython. Then make sure a valid device tree is sent through via qemu.

@ewenmcneill
Copy link
Contributor

@stffrdhrn Yes, @mithro had already suggested MicroPython parse DeviceTree to find things (rather than the current method which is basically "compiling in" things learnt by essentially #include <generated/csr.h> -- the reason why I commented on this ticket. There seems to be general agreement that's a good direction for MicroPython to explore, but no one has implemented code so I don't think "runtime DeviceTree" is happening in MIcroPython soon...

It would also help if the litex BIOS also could parse DeviceTree at least to find the things it needs to initialise. But I'm aware (from IRC) the litex BIOS currently doesn't fit in the space available (32kB) on some platform/CPU combinations, so there's not much room for more things in there right now, which might delay "runtime DeviceTree" for the litex BIOS. (MicroPython is also fairly space constrained in general, but I think less so on code that is ROMable -- ie, doesn't have to fit in RAM -- as the litex platforms treat MicroPython as a post-BIOS application, which potentially gets the rest of the flash space).

For the qemu case, I think we still need some short term solution, that allows building the emulated devices at a "known" location. It might make sense to pass that "known location" in via DeviceTree (and perhaps extract it out at build time) as an intermediate step? With the medium term goal perhaps being just that qemu puts things where it likes, and then provides information on where they are via DeviceTree parsed at run time.

I'm thinking this "compile time" DeviceTree might also be the intermediate step for MicroPython, to at least stop copying around generated/... header files on every build.

Does that make sense?

Ewen

CarlFK added a commit to CarlFK/litex-buildenv that referenced this issue Sep 10, 2018
@mithro mithro closed this as completed in 96a2077 Sep 11, 2018
mithro added a commit to mithro/litex-buildenv that referenced this issue Sep 30, 2018
 * litedram changed from ea1ac4d to 5820970
    * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * litex changed from v0.1-451-g537b0e90 to v0.1-492-g934a5da5
    * 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec>
    *   9097573e - Merge pull request timvideos#109 from cr1901/xip-improve <enjoy-digital>
    |\
    | * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones>
    | * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones>
    | * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones>
    * | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec>
    * | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec>
    * | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec>
    * | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec>
    * | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec>
    * | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec>
    * | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec>
    * | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec>
    * | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec>
    |/
    * 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec>
    * 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec>
    * 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec>
    * 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec>
    * b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec>
    * 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec>
    * 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec>
    * c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec>
    * 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec>
    * e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec>
    * e9ed7370 - ease RemoteClient import <Florent Kermarrec>
    *   346dcf94 - Merge pull request timvideos#108 from xobs/use-csr-accessors <enjoy-digital>
    |\
    | * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross>
    | * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross>
    * |   1c1d87f8 - Merge pull request timvideos#106 from cr1901/data-crt0 <Tim Ansell>
    |\ \
    | |/
    | * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones>
    |/
    * 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec>
    * 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec>
    * cde72603 - targets/sim: generate csr.csv <Florent Kermarrec>
    * f62df502 - targets/sim: add rom-init <Florent Kermarrec>
    * 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec>
    * 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec>
    * a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec>
    * 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec>
    * bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec>
    * badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 58209708e74999c567389fc514c40acfd739d0a6 litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 934a5da559a591f92f592dcd3d1bb676218f9796 litex (v0.1-492-g934a5da5)
 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)
@ray-bot ray-bot bot added the in-progress label Sep 30, 2018
mithro added a commit to mithro/litex-buildenv that referenced this issue Sep 30, 2018
 * litedram changed from ea1ac4d to 5820970
    * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * litex changed from v0.1-451-g537b0e90 to v0.1-492-g934a5da5
    * 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec>
    *   9097573e - Merge pull request timvideos#109 from cr1901/xip-improve <enjoy-digital>
    |\
    | * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones>
    | * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones>
    | * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones>
    * | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec>
    * | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec>
    * | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec>
    * | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec>
    * | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec>
    * | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec>
    * | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec>
    * | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec>
    * | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec>
    |/
    * 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec>
    * 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec>
    * 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec>
    * 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec>
    * b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec>
    * 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec>
    * 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec>
    * c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec>
    * 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec>
    * e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec>
    * e9ed7370 - ease RemoteClient import <Florent Kermarrec>
    *   346dcf94 - Merge pull request timvideos#108 from xobs/use-csr-accessors <enjoy-digital>
    |\
    | * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross>
    | * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross>
    * |   1c1d87f8 - Merge pull request timvideos#106 from cr1901/data-crt0 <Tim Ansell>
    |\ \
    | |/
    | * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones>
    |/
    * 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec>
    * 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec>
    * cde72603 - targets/sim: generate csr.csv <Florent Kermarrec>
    * f62df502 - targets/sim: add rom-init <Florent Kermarrec>
    * 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec>
    * 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec>
    * a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec>
    * 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec>
    * bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec>
    * badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 58209708e74999c567389fc514c40acfd739d0a6 litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 934a5da559a591f92f592dcd3d1bb676218f9796 litex (v0.1-492-g934a5da5)
 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)
mithro added a commit to mithro/litex-buildenv that referenced this issue Oct 1, 2018
 * litedram changed from ea1ac4d to 41a8a24
    * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec>
    * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec>
    * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec>
    * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec>
    * 1bc016c - test: add test_examples <Florent Kermarrec>
    * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec>
    * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec>
    *   70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * | 71f78d9 - Fix reordering controller rejecting all commands <>
    * | 8f14211 - Account for CWL in write to read timing <>
    |/
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * litex changed from v0.1-451-g537b0e90 to v0.1-494-g6e327cda
    * 6e327cda - bios/sdram: rewrite write_leveling (simplify and improve robustness) <Florent Kermarrec>
    * 975be668 - platforms/genesys2: add eth clock timing constraint <Florent Kermarrec>
    * 934a5da5 - soc/cores/clock: add expose_drp on S7PLL/S7MMCM <Florent Kermarrec>
    *   9097573e - Merge pull request timvideos#109 from cr1901/xip-improve <enjoy-digital>
    |\
    | * 0ff6d586 - Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section). <William D. Jones>
    | * 81060081 - integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM. <William D. Jones>
    | * db906190 - integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX). <William D. Jones>
    * | 082b0301 - targets: use new clock abstraction on all 7-series targets <Florent Kermarrec>
    * | 74e74dc0 - soc/cores/clock: different clkin_freq_range for pll and mmcm <Florent Kermarrec>
    * | 91d8cc2d - soc/cores/clock: different vco_freq_range for pll and mmcm <Florent Kermarrec>
    * | 6cd95494 - soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) <Florent Kermarrec>
    * | 912ca323 - soc/cores/clock: create specific S7IDELAYCTRL module <Florent Kermarrec>
    * | baec87f5 - soc/cores/clock: add S7MMCM support <Florent Kermarrec>
    * | ef405249 - soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) <Florent Kermarrec>
    * | 5415b521 - targets/arty: use new clock abstraction module (compile, untested on board) <Florent Kermarrec>
    * | 63fc3950 - soc/cores: init clock abstraction module <Florent Kermarrec>
    |/
    * 70a32ed8 - sim/verilator: add multithread support (default=1) <Florent Kermarrec>
    * 7f0d116d - soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now) <Florent Kermarrec>
    * 22febe95 - boards/targets: uniformize things between targets <Florent Kermarrec>
    * 01b025aa - soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication <Florent Kermarrec>
    * b528a005 - cores/cpu: add software informations to cpu and simplify cpu_interface <Florent Kermarrec>
    * 2d785cb0 - boards/plarforms: fix issues found while testing simple design on all platforms <Florent Kermarrec>
    * 0b0e3ac1 - test/test_targets: test simple design with all platforms <Florent Kermarrec>
    * c88029d3 - soc_core: add uart-stub argument <Florent Kermarrec>
    * 0d2d3959 - setup.py: add litex_simple exec (to ease building simple design) <Florent Kermarrec>
    * e04530e0 - test/test_targets: update and reorganize targets <Florent Kermarrec>
    * e9ed7370 - ease RemoteClient import <Florent Kermarrec>
    *   346dcf94 - Merge pull request timvideos#108 from xobs/use-csr-accessors <enjoy-digital>
    |\
    | * 6f25a0d8 - csr: use external csr_readl()/csr_writel() if present <Sean Cross>
    | * 9a252e36 - csr: use readl()/writel() accessors for accessing mmio <Sean Cross>
    * |   1c1d87f8 - Merge pull request timvideos#106 from cr1901/data-crt0 <Tim Ansell>
    |\ \
    | |/
    | * 9d4da737 - libbase/crt0-lm32.S: Add provisions for loading .data from flash. <William D. Jones>
    |/
    * 01ae7d42 - README: add migen/litex clarification <Florent Kermarrec>
    * 15e584d8 - targets/sim: generate analyzer.csv <Florent Kermarrec>
    * cde72603 - targets/sim: generate csr.csv <Florent Kermarrec>
    * f62df502 - targets/sim: add rom-init <Florent Kermarrec>
    * 1dbf591e - targets/sim: add ram-init param to allow initializing ram from file (faster than tftp) <Florent Kermarrec>
    * 9893c246 - integration/soc_core: add get_mem_data function to read memory content from file <Florent Kermarrec>
    * a3eb2e40 - soc/intergration/builder: fix when no sdram <Florent Kermarrec>
    * 934b08ed - targets/sim: merge in a single class and ease configuration <Florent Kermarrec>
    * bd42b188 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    * 3e77ae78 - targets: replace MiniSoC with EthernetSoC <Florent Kermarrec>
    * badd9924 - targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server) <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 41a8a246b65460fd1abe86d39a4107c349ad60e4 litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)
@ray-bot ray-bot bot added done and removed in-progress labels Oct 1, 2018
@ray-bot
Copy link

ray-bot bot commented Oct 1, 2018

Hey, Your issue has been resolved 🎉, Thanks!

mithro added a commit to mithro/litex-buildenv that referenced this issue Oct 1, 2018
 * litedram changed from ea1ac4d to 208f556
    *   208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec>
    | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec>
    | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec>
    | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec>
    | * 1bc016c - test: add test_examples <Florent Kermarrec>
    | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec>
    | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec>
    * | 69eaf84 - Fix DDR2 and below compilation failure <>
    |/
    *   70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * | 71f78d9 - Fix reordering controller rejecting all commands <>
    * | 8f14211 - Account for CWL in write to read timing <>
    |/
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-172-g56f359d
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 208f5562d1e3825ddac6e73d14394d3310f2d239 litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
 56f359d6dc5fff01b36796c8667dd4b58c0428c9 migen (0.6.dev-172-g56f359d)
@mithro
Copy link
Member

mithro commented Oct 2, 2018

@CarlFK Can you confirm this is fixed now?

mithro added a commit to mithro/litex-buildenv that referenced this issue Oct 2, 2018
 * litedram changed from ea1ac4d to eddce76
    * eddce76 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell>
    *   208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec>
    | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec>
    | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec>
    | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec>
    | * 1bc016c - test: add test_examples <Florent Kermarrec>
    | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec>
    | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec>
    * | 69eaf84 - Fix DDR2 and below compilation failure <>
    |/
    *   70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * | 71f78d9 - Fix reordering controller rejecting all commands <>
    * | 8f14211 - Account for CWL in write to read timing <>
    |/
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b
    * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski>
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 eddce76ee4a5bdb84e09020983aaa273b9cd5342 litedram (heads/master)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
 d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)
mithro added a commit to mithro/litex-buildenv that referenced this issue Oct 2, 2018
 * litedram changed from ea1ac4d to 6c7a804
    * 6c7a804 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell>
    *   208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec>
    | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec>
    | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec>
    | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec>
    | * 1bc016c - test: add test_examples <Florent Kermarrec>
    | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec>
    | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec>
    * | 69eaf84 - Fix DDR2 and below compilation failure <>
    |/
    *   70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * | 71f78d9 - Fix reordering controller rejecting all commands <>
    * | 8f14211 - Account for CWL in write to read timing <>
    |/
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b
    * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski>
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 6c7a804986d8916bdc3d97ba2181c00787a5a91b litedram (heads/master)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
 d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)
mithro added a commit to mithro/litex-buildenv that referenced this issue Oct 2, 2018
 * litedram changed from ea1ac4d to 5b02791
    * 5b02791 - modules: add tCCD to all modules <Florent Kermarrec>
    * 6c7a804 - Adding tCCD for DDR2 modules. <Tim 'mithro' Ansell>
    *   208f556 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 41a8a24 - modules: express tFAW in ns <Florent Kermarrec>
    | * 7062068 - modules: split DDR3 in 2 categories: Chips and SO-DIMMs <Florent Kermarrec>
    | * 0f46dc4 - modules: add DDR3-800 timings for MT41J128M16 and use it on arty example <Florent Kermarrec>
    | * 426ae23 - examples/litedram_gen: add sdram_module_speedgrade parameter <Florent Kermarrec>
    | * 1bc016c - test: add test_examples <Florent Kermarrec>
    | * f7f8169 - test: update downconverter/upconverter <Florent Kermarrec>
    | * 8de1d91 - core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) <Florent Kermarrec>
    * | 69eaf84 - Fix DDR2 and below compilation failure <>
    |/
    *   70516c4 - Merge branch 'master' of https://github.com/enjoy-digital/litedram <>
    |\
    | * 5820970 - frontend/crossbar: fix timvideos#49 <Florent Kermarrec>
    * | 71f78d9 - Fix reordering controller rejecting all commands <>
    * | 8f14211 - Account for CWL in write to read timing <>
    |/
    * 5fb8afe - frontend/axi: omit bank in rdata connect <Florent Kermarrec>
    *   06ca53d - Merge pull request timvideos#48 from enjoy-digital/staging <enjoy-digital>
    |\
    | *   5a4d063 - Merge branch 'master' into staging <enjoy-digital>
    | |\
    | |/
    |/|
    * | 5984eaa - core: change api for out-of-order. (with_reordering passed to controller and not ports). <Florent Kermarrec>
    * | 6e10dae - core/bankmachine/write to precharge: indicate that AL=0 <Florent Kermarrec>
    * |   869c8ee - Merge pull request timvideos#46 from enjoy-digital/WritePrechargeFix <enjoy-digital>
    |\ \
    | * | 0405f41 - Update the write-to-precharge timings so it works with 1:2 <>
    * | | 30c32f5 - example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) <Florent Kermarrec>
    |/ /
    * | 2a3cacb - core/bankmachine: minor cleanup on trc/tras <Florent Kermarrec>
    * |   42ccf05 - Merge pull request timvideos#45 from enjoy-digital/tRAS_FIX <enjoy-digital>
    |\ \
    | * | 79b1421 - Auto precharge is too pessimistic, it will wait on its own for a valid time to execute <John Sully>
    | * | 177d739 - Implement tRAS <John Sully>
    * | |   5902027 - Merge pull request timvideos#44 from enjoy-digital/tRC_Fix <enjoy-digital>
    |\ \ \
    | |/ /
    | * | 5f6b857 - This adds support for tRC timing parameters <John Sully>
    |/ /
    * |   1777720 - Merge pull request timvideos#42 from enjoy-digital/HalfRateSequentialFix <enjoy-digital>
    |\ \
    | * | 06c8c2a - The actual fix <John Sully>
    | * | e22580f - remove unnecessary file <John Sully>
    | * | c028786 - Fix overflow bug from code review <John Sully>
    | * | 8447d69 - We wait an extra cycle for no reason <John Sully>
    |/ /
    | *   04aa04d - Merge pull request timvideos#43 from enjoy-digital/EfficencyFixes <enjoy-digital>
    | |\
    |/ /
    | * c4bd842 - Fix many bugs <John Sully>
    | * fa0f3b2 - Use the ready signal for cas_allowed so that arbitrators know not to iterate <John Sully>
    |/
    * c12404e - README: Add ECC <Florent Kermarrec>
    * 3f4c14b - frontend/ecc: expose incident bits, change clear register name <Florent Kermarrec>
    * b9aadf1 - frontend/axi: remove write buffer reservation (not needed) <Florent Kermarrec>

 * liteeth changed from 3d86844 to 40b99ec
    * 40b99ec - test: use new RemoteClient import <Florent Kermarrec>
    * c370e9f - phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) <Florent Kermarrec>

 * litepcie changed from 3e8de2d to a09d225
    * a09d225 - test: use new RemoteClient import <Florent Kermarrec>

 * litesata changed from fb72044 to b78a731
    * b78a731 - test: use new RemoteClient import <Florent Kermarrec>

 * litescope changed from 686db4f to 1634fa3
    * 1634fa3 - test: use new RemoteClient import <Florent Kermarrec>
    * cb27987 - examples/make: look for platform in migen if not present in litex <Florent Kermarrec>

 * migen changed from 0.6.dev-168-gca0df1c to 0.6.dev-173-gd3b875b
    * d3b875b - Fixed on board green led pin number. Added "multi" led. <Piotr Esden-Tempski>
    * 56f359d - Added icebreaker platform. (timvideos#135) <Piotr Esden-Tempski>
    * 88e72a5 - Sayma RTM: expose clock mezzanine gpio as a connector (timvideos#134) <hartytp>
    * 1d3433e - Revert "Emit `default_nettype none." <Sebastien Bourdeauducq>
    * 4621abc - sayma rtm: add clock mezzanine GPIO (timvideos#133) <hartytp>

Full submodule status
--
 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 5b02791580db9d1bae64b6524b7aca3540d89937 litedram (remotes/origin/HEAD)
 40b99ecc05ee490d77477cba542db6d63333c390 liteeth (remotes/origin/HEAD)
 a09d225aafbf98b36913e10366f64ccfad3304af litepcie (remotes/origin/HEAD)
 b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
 1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
 6e327cda2697d37b23f607a5a7712363dc60857a litex (v0.1-494-g6e327cda)
 d3b875b46eee4d34e093e63cd769bdfaae0da3df migen (0.6.dev-173-gd3b875b)
@ray-bot ray-bot bot removed the in-progress label Oct 2, 2018
@ray-bot
Copy link

ray-bot bot commented Oct 2, 2018

Hey, Your issue has been resolved 🎉, Thanks!

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

No branches or pull requests

4 participants