[Mellanox] add new platform msn2201

[tomer-israel]

Signed-off-by: tomeri tomeri@nvidia.com

Why I did it

add new files for the new platform MSN2201

How I did it

added new device folder and platform device files to it based on (msn2700)
some of the files are linked to msn2700 and some were changed according to the new device specification (ports, speeds)

How to verify it

run with these files on the new HW

Which release branch to backport (provide reason below if selected)

• 201811
• 201911
• 202006
• 202012
• 202106

Description for the changelog

A picture of a cute animal (not mandatory but encouraged)

[dprital]

Please remove the backport from 202012.

[dprital]

Please add NVIDIA Copyright header for the files

[keboliu]

1. Currently all other existing platforms are all installed with SFP cages, this is the first time we have RJ45, so in platform API chassis object initialization, it should ignore the RJ45 ports. You may need to start from here to check https://github.com/Azure/sonic-buildimage/blob/master/platform/mellanox/mlnx-platform-api/sonic_platform/chassis.py#L68
2. You need to fill in device data for 2201 in https://github.com/Azure/sonic-buildimage/blob/master/platform/mellanox/mlnx-platform-api/sonic_platform/device_data.py

[moshemos]

1. Buffer configuration. Should be approved by @stephen Sun - Done! should be as SN2700
2. How can pcied is provided? Who provided the info on the new system? was Yehuda and his team confirmed it? this is no Nvidia switch but rather a DNI switch so it might be the same and might not.
3. Is the default speed of the ports is 1G and not 100M? is this aligned with the MRD?
4. SAI profile was approved by Itai? No - Sai will be supported 2 days after Itay will get the platform for bring up
5. device/mellanox/x86_64-mlnx_msn2201-r0/platform.json:
   a. Product name is 2700. Wrong.
   b. Are there 3 CPLD files for this system? who confirmed?
   c. Fans configuration – who confirmed? It was not tested to real hw
   d. Psu configuration – who confirmed? It was not tested to real hw
   e. Thermal configuration – who confirmed? It was not tested to real hw
   f. 1G/100M should be supported. Missing 100m support for all ports. Not aligned with the mrd.
6. device/mellanox/x86_64-mlnx_msn2201-r0/platform_components.json
   There is an assumption we are upble to upgrade them. Was this discussed with Yehuda? Are the tools used today are good enough? there is open item on the alligator weekly which is not solved yet.
7. device/mellanox/x86_64-mlnx_msn2201-r0/sensors.conf
   a. Device name is 2700. Wrong.
   b. As there is no real hw how these file is generated?

[tomer-israel]

1. Buffer configuration. Should be approved by @stephen Sun - Done! should be as SN2700
2. How can pcied is provided? Who provided the info on the new system? was Yehuda and his team confirmed it? this is no Nvidia switch but rather a DNI switch so it might be the same and might not.
3. Is the default speed of the ports is 1G and not 100M? is this aligned with the MRD?
4. SAI profile was approved by Itai? No - Sai will be supported 2 days after Itay will get the platform for bring up
5. device/mellanox/x86_64-mlnx_msn2201-r0/platform.json:
   a. Product name is 2700. Wrong.
   b. Are there 3 CPLD files for this system? who confirmed?
   c. Fans configuration – who confirmed? It was not tested to real hw
   d. Psu configuration – who confirmed? It was not tested to real hw
   e. Thermal configuration – who confirmed? It was not tested to real hw
   f. 1G/100M should be supported. Missing 100m support for all ports. Not aligned with the mrd.
6. device/mellanox/x86_64-mlnx_msn2201-r0/platform_components.json
   There is an assumption we are upble to upgrade them. Was this discussed with Yehuda? Are the tools used today are good enough? there is open item on the alligator weekly which is not solved yet.
7. device/mellanox/x86_64-mlnx_msn2201-r0/sensors.conf
   a. Device name is 2700. Wrong.
   b. As there is no real hw how these file is generated?

1. done
2. Yehuda's team gave us the values of the pcie
3. the default speed is 1G, according to Haim Raz: "Always max, 1G for the RJ45 base-t and 100G for the qsfp-28."
4. on the sai xml the "port-speed" for the RJ-45 is unknown, itai needs to supply the port-speed for the rj45
5. i discussed with the hw-management team about the values: cpld, fans, psu, thermal values should be fine.
   about the 1g/100m speeds on dynamic port breakout: I didnt add the 100M for the DPB , I have a different PR for this support and we need to think if the 100M is needed for the DPB mode.
   Add support for RJ45 speeds on dynamic breakout mode #9
6. I will take it with Yehuda
7. new file was received from hw-management

[liat-grozovik]

Please check with Vadim/Michael that we can use all the ports for thermal. Not sure that the ports which are RJ45 are. maybe we can specific a range of the 4 100g ports only?

[tomer-israel]

RJ45 don't have thermals.
I will change it to, so we need to change it to:
THERMAL_DEV_CATEGORY_MODULE:(52, 4)

I will test it and update it

[liat-grozovik]

Please check with Vadim/Michael if this is the right definition for termal. I am not aware we got a clear statement.

[tomer-israel]

answer from vadim:
"Regarding “minimum_table” – as far as I know we didn’t get dynamic minimum table for Alligator yet. In hw-mgmt thermal algorithm we consider all corners to be at 60%."

[liorghub]

Code taken to:
liorghub#20