hdl

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Here are 84 public repositories matching this topic...

chipsalliance / sv-tests

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Test suite designed to check compliance with the SystemVerilog standard.

rtl verilog systemverilog hdl compliance-testing symbiflow

Updated Mar 21, 2025
SystemVerilog

tymonx / logic

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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

BrianHGinc / BrianHG-DDR3-Controller

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DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3

Updated Apr 8, 2024
SystemVerilog

tymonx / virtio

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Virtio implementation in SystemVerilog

cmake fpga model rtl verilog xilinx vivado systemverilog systemc hdl virtio verilator quartus

Updated Jan 23, 2018
SystemVerilog

shehanmunasinghe / tinyGPU

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tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

gpu simd systemverilog hdl computer-organization processor-design

Updated Jul 14, 2021
SystemVerilog

adamchristiansen / fpga-ethernet-udp

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An HDL design for sending data over Ethernet

mac fpga udp ipv4 ip ethernet hdl mii phy

Updated May 8, 2023
SystemVerilog

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy

Updated Nov 6, 2022
SystemVerilog

bensampson5 / libsv

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An open source, parameterized SystemVerilog digital hardware IP library

asic fpga hardware ip verilog systemverilog hardware-designs hardware-libraries hdl digital-design asic-library fpga-library

Updated May 26, 2024
SystemVerilog

SkyworksSolutionsInc / fplib

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Fixed point math library for SystemVerilog

verilog systemverilog hdl fixedpoint fixed-point-arithmetic

Updated Nov 14, 2024
SystemVerilog

dpretet / svlogger

Sponsor

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SystemVerilog Logger

asic fpga simulation logger logging class verilog systemverilog hdl icarus

Updated Nov 14, 2022
SystemVerilog

GabbedT / ApogeoRV

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A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

asic cpu fpga systemverilog hdl rv32i rv32c rv32m rv32b rv32zfinx

Updated Mar 2, 2025
SystemVerilog

hotwolf / WbXbc

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HDL components to build a customized Wishbone crossbar switch

verilog hdl wishbone crossbar

Updated May 30, 2019
SystemVerilog

semify-eda / go.debug

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Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

verification eda verilog systemverilog hdl uvm testbench verilator

Updated Oct 14, 2021
SystemVerilog

rubinsteina13 / SV_I2S_RX_CORE

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Synthesizable SystemVerilog IP-Core of the I2S Receiver

fpga verilog systemverilog hdl system-verilog cpld i2s i2s-dac ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

nockieboy / YM2149_PSG_system

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YM2149 / AY-3-8910 Programmable Sound Generator in SystemVerilog and Verilog. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built-in floating point system clock divider/generator.

fpga verilog retrocomputing systemverilog hdl psg ay-3-8910 ym2149 sound-generator