A Compiler for the Popr Language
CHO is a benchmark suite for OpenCL FPGA Accelerators
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
HLS SHA-3 Accelerator
Finding bugs in high-level synthesis tools using Csmith to generate random, valid C programs.
Signature Based Fault Tolerance
Laboratory exercises on cards with ARM, FPGA and sensors
A RISC-V core for my high level synthesis compiler
Laboratory exercises on cards with ARM, FPGA and sensors for "Embedded System Design" course NTUA 2020 -2021
A MonteCarlo light propagation algorithm on a Xilinx FPGA using High Level Synthesis.
A partial, synthesizable reimplementation of the C standard library
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