XLS: Accelerated HW Synthesis

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

FPGA Accelerator for CNN using Vivado HLS

PandA-bambu public repository

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

Tutorials on HLS Design

A graph linear algebra overlay

HeteroCL-MLIR dialect for accelerator design

FPGA acceleration of arbitrary precision floating point computations.

HLS for Networks-on-Chip

Near-storage compute aware file system and FPGA operator pipelines.

Monte Carlo Methods applied to the Black-Scholes financial market model

AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!

Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis

Fast Floating Point Operators for High Level Synthesis

Convert C files into Verilog