Merge branch 'coredsl_exceptions' into coverage

tum-ei-eda · Apr 4, 2024 · 24188ac · 24188ac
2 parents a5c1bd9 + a407d47
commit 24188ac
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/m2isar/backends/etiss/instruction_transform.py b/m2isar/backends/etiss/instruction_transform.py
@@ -554,6 +554,7 @@ def slice_operation(self: behav.SliceOperation, context: TransformerContext):
 	try:
 		new_size = int(left.code.replace("U", "").replace("L", "")) - int(right.code.replace("U", "").replace("L", "")) + 1
 		mask = (1 << (int(left.code.replace("U", "").replace("L", "")) - int(right.code.replace("U", "").replace("L", "")) + 1)) - 1
+		mask = f"{mask}ULL"
 
 	# slice with actual lower and upper bound code if not possible to slice with integers
 	except ValueError:

diff --git a/m2isar/backends/etiss/templates/etiss_arch_cpp.mako b/m2isar/backends/etiss/templates/etiss_arch_cpp.mako
@@ -126,10 +126,13 @@ void ${core_name}Arch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
 <% ref = "*" if len(reg.children) > 0 else "" %> \
 	% if reg.range.length > 1:
 	% for idx, val in reg._initval.items():
-	${ref}${core_name.lower()}cpu->${reg.name}[${idx}] = ${val};
+<% suffix = "ULL" if val > 0 else "LL" %> \
+	${ref}${core_name.lower()}cpu->${reg.name}[${idx}] = ${val}${suffix};
 	% endfor
 	% else:
-	${ref}${core_name.lower()}cpu->${reg.name} = ${reg._initval[None]};
+<% val = reg._initval[None] %> \
+<% suffix = "ULL" if val > 0 else "LL" %> \
+	${ref}${core_name.lower()}cpu->${reg.name} = ${val}${suffix};
 	% endif
 	% endfor