Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

[jerryz123]

Related PRs / Issues:

• Scala bump 2.13 riscv-boom/riscv-boom#626
• Bump to scala 2.13 constellation#34
• Bump to scala 2.13 cva6-wrapper#16
• Fix for scala 2.13 FFTGenerator#4
• Bump to scala 2.13/new rocketchip gemmini#270
• Bump to scala 2.13/chisel 3.5.5/new rocketchip hwacha#42
• Bump to scala2.13 ibex-wrapper#3
• Bump to scala 2.13/chisel 3.5.5/latest rocketchip firesim/icenet#36
• Bump to scala 2.13/chisel 3.5.5/latest rocketchip riscv-sodor#74
• Bump to chisel 3.5.5 sha3#36
• Bump to scala 2.13/chisel 3.5.5/latest rocketchip chipsalliance/rocket-chip-blocks#10
• Bump to scala 2.13 chipsalliance/rocket-chip-inclusive-cache#8
• Bump to scala 2.13/chisel 3.5.5/latest rocketchip testchipip#154
• Bump to scala2.13/chisel 3.5.5/latest rocketchip rocket-dsp-utils#10
• Bump to scala 2.13/chisel 3.5.5/latest rocketchip chipsalliance/rocket-chip-fpga-shells#9
• Assorted fixes for scala 2.13/chisel 3.5.5 chipsalliance/rocket-chip#3196
• Bump to latest rocket-chip/scala2.13 firesim/firesim#1392

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[sagark]

LGTM