ucb-bar · jerryz123 · Mar 16, 2023 · Mar 8, 2023 · Mar 9, 2023 · Mar 9, 2023
diff --git a/generators/testchipip b/generators/testchipip
diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh
@@ -111,4 +111,10 @@ if [ $TOOLCHAIN == "riscv-tools" ]; then
     make -C $RDIR/generators/gemmini/software/libgemmini install
 fi
 
+echo '==>  Installing DRAMSim2 Shared Library'
+cd $RDIR
+cd tools/DRAMSim2
+make libdramsim.so
+cp libdramsim.so $RISCV/lib/
+
 echo "Extra Toolchain Utilities/Tests Build Complete!"
diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile
@@ -0,0 +1,138 @@
+#########################################################################################
+# xcelium makefile
+#########################################################################################
+
+define CAD_INFO_HEADER
+# --------------------------------------------------------------------------------
+# This script was written and developed by Chipyard at UC Berkeley; however, the
+# underlying commands and reports are copyrighted by Cadence. We thank Cadence for
+# granting permission to share our research to help promote and foster the next
+# generation of innovators.
+# --------------------------------------------------------------------------------
+endef
+
+export CAD_INFO_HEADER
+
+#########################################################################################
+# general path variables
+#########################################################################################
+base_dir=$(abspath ../..)
+sim_dir=$(abspath .)
+
+#########################################################################################
+# include shared variables
+#########################################################################################
+include $(base_dir)/variables.mk
+
+#########################################################################################
+# name of simulator (used to generate *.f arguments file)
+#########################################################################################
+sim_name = xrun
+
+#########################################################################################
+# xcelium simulator types and rules
+#########################################################################################
+sim_prefix = simx
+sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
+sim_debug = $(sim)-debug
+sim_workdir = $(sim).xcelium.d
+sim_run_tcl = $(sim)_run.tcl
+sim_debug_run_tcl = $(sim_debug)_run.tcl
+
+include $(base_dir)/xcelium.mk
+
+.PHONY: default debug
+default: $(sim)
+debug: $(sim_debug)
+
+#########################################################################################
+# simulation requirements
+#########################################################################################
+SIM_FILE_REQS += \
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
+
+# copy files but ignore *.h files in *.f since xcelium has -Wcxx include
+$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
+	cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
+	$(foreach file,\
+		$(SIM_FILE_REQS),\
+		$(if $(filter %.h,$(file)),\
+			,\
+			echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
+
+#########################################################################################
+# import other necessary rules and variables
+#########################################################################################
+include $(base_dir)/common.mk
+
+#########################################################################################
+# xcelium binary and arguments
+#########################################################################################
+XCELIUM = xrun
+XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
+
+#########################################################################################
+# xcelium build paths
+#########################################################################################
+model_dir = $(build_dir)/$(long_name)
+model_dir_debug = $(build_dir)/$(long_name).debug
+
+
+#########################################################################################
+# xcelium simulator rules
+#########################################################################################
+
+$(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
+	rm -rf $(model_dir)
+	$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
+
+$(sim_run_tcl): $(sim_workdir)
+	echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
+	echo "run" >> $(sim_run_tcl)
+	echo "exit" >> $(sim_run_tcl)
+
+$(sim): $(sim_workdir) $(sim_run_tcl)
+	echo "#!/usr/bin/env bash" > $(sim)
+	echo "$$CAD_INFO_HEADER" >> $(sim)
+	cat arg-reshuffle >> $(sim)
+	echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
+	chmod +x $(sim)
+
+$(sim_debug_run_tcl): $(sim_workdir)
+	echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
+	echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
+	echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
+	echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
+	echo "run" >> $(sim_debug_run_tcl)
+	echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
+	echo "exit" >> $(sim_debug_run_tcl)
+
+
+$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
+	echo "#!/usr/bin/env bash" > $(sim_debug)
+	echo "$$CAD_INFO_HEADER" >> $(sim_debug)
+	cat arg-reshuffle >> $(sim_debug)
+	echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
+	echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
+	chmod +x $(sim_debug)
+
+
+#########################################################################################
+# create vcd rules
+#########################################################################################
+.PRECIOUS: $(output_dir)/%.vcd %.vcd
+$(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
+	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
+
+#########################################################################################
+# general cleanup rules
+#########################################################################################
+.PHONY: clean clean-sim clean-sim-debug
+clean:
+	rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
+
+clean-sim:
+	rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log
+
+clean-sim-debug:
+	rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_workdir) $(sim_debug_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log
diff --git a/sims/xcelium/arg-reshuffle b/sims/xcelium/arg-reshuffle
@@ -0,0 +1,21 @@
+
+regular_args=""
+target_args="+permissive"
+for var in "$@"
+do
+    if [[ $var = -* ]] || [[ $var = +* ]]
+    then
+        if [[ $var = +vcdfile=* ]]
+        then
+            XCELIUM_WAVEFORM_FLAG=${var/+vcdfile=/""}
+        else
+            regular_args="$regular_args $var"
+        fi
+    else
+        target_args="$target_args +target-argument=$var"
+    fi
+done
+target_args="$target_args +permissive-off"
+
+INPUT_ARGS="$regular_args $target_args"
+
diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim
diff --git a/xcelium.mk b/xcelium.mk
@@ -0,0 +1,65 @@
+
+WAVEFORM_FLAG=+vcdfile=$(sim_out_name).vcd
+
+# If ntb_random_seed unspecified, xcelium uses 1 as constant seed.
+# Set ntb_random_seed_automatic to actually get a random seed
+ifdef RANDOM_SEED
+SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
+else
+SEED_FLAG=+ntb_random_seed_automatic
+endif
+
+CLOCK_PERIOD ?= 1.0
+RESET_DELAY ?= 777.7
+
+#----------------------------------------------------------------------------------------
+# gcc configuration/optimization
+#----------------------------------------------------------------------------------------
+include $(base_dir)/sims/common-sim-flags.mk
+
+
+XC_CXX_PREFIX=-Wcxx,
+XC_LD_PREFIX=-Wld,
+
+REMOVE_RPATH=-Wl,-rpath%
+
+XCELIUM_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS))
+XCELIUM_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS)))
+
+XCELIUM_COMMON_ARGS = \
+	-64bit \
+	-xmlibdirname $(sim_workdir) \
+	-l /dev/null \
+	-log_xmsc_run /dev/null
+
+XCELIUM_CC_OPTS = \
+	$(XCELIUM_CXXFLAGS) \
+	$(XCELIUM_LDFLAGS) \
+	-enable_rpath
+
+XCELIUM_NONCC_OPTS = \
+	-fast_recompilation \
+	-top $(TB) \
+	-sv \
+	-ALLOWREDEFINITION \
+	-timescale 1ns/10ps \
+	-define INTCNOPWR \
+	-define INTC_NO_PWR_PINS \
+	-define INTC_EMULATION \
+	-f $(sim_common_files) \
+	-glsperf \
+	-notimingchecks \
+	-delay_mode zero
+
+PREPROC_DEFINES = \
+	-define XCELIUM \
+	-define CLOCK_PERIOD=$(CLOCK_PERIOD) \
+	-define RESET_DELAY=$(RESET_DELAY) \
+	-define PRINTF_COND=$(TB).printf_cond \
+	-define STOP_COND=!$(TB).reset \
+	-define MODEL=$(MODEL) \
+	-define RANDOMIZE_MEM_INIT \
+	-define RANDOMIZE_REG_INIT \
+	-define RANDOMIZE_GARBAGE_ASSIGN \
+	-define RANDOMIZE_INVALID_ASSIGN
+
+1 −1		ci-tests/testlib.c
+4 −2		fesvr/elfloader.cc
+42 −15		fesvr/htif.cc
+7 −3		fesvr/htif.h
+3 −2		riscv/cfg.h
+50 −30		riscv/clint.cc
+4 −0		riscv/csrs.cc
+56 −76		riscv/debug_module.cc
+3 −6		riscv/debug_module.h
+2 −2		riscv/decode.h
+2 −2		riscv/decode_macros.h
+40 −14		riscv/devices.h
+2 −5		riscv/insns/cm_mva01s.h
+3 −5		riscv/insns/cm_mvsa01.h
+23 −5		riscv/interactive.cc
+7 −0		riscv/isa_parser.cc
+24 −7		riscv/mmu.cc
+7 −6		riscv/mmu.h
+16 −31		riscv/plic.cc
+5 −2		riscv/sim.cc
+6 −0		riscv/sim.h
+7 −7		riscv/triggers.cc
+1 −1		spike_main/spike-log-parser.cc
+22 −4		spike_main/spike.cc