Chipyard 1.10.0 Release

Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop. FireSim bumped with new local FPGA support: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims.

Added

• QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in #1399
• New Scala-based Config Finder by @abejgonzalez in #1424
• ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in #1439
• Add mt-helloworld example by @jerryz123 in #1428
• Add tutorial software by @abejgonzalez in #1447
• Support not instantiating the TileClockGater/ResetSetter PRCI control by @jerryz123 in #1459
• ELF-based-loadmem | architectural restartable checkpoints by @jerryz123 in #1438
• Add embench build support by @jerryz123 in #1479
• Support multi-run of binaries by @jerryz123 in #1480
• Integrate barf (prefetchers) by @jerryz123 in #1505
• Add higher level explanations of RoCC + more resources by @nikhiljha in #1486
• Support banked/partitioned scratchpads by @jerryz123 in #1431
• Add dual-issue in-order "shuttle" core by @jerryz123 in #1495
• Improve peripheral fragments to include more peripheral devices and support instantiating multiple instances of same device by @T-K-233 in #1511

Changed

• Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in #1411
• Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in #1430
• PLL integration example + FlatChipTop/TestHarness by @jerryz123 in #1427
• bump testchipip by @joey0320 in #1434
• Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in #1436
• Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in #1435
• Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in #1446
• Bump to Hammer 1.1.1 by @harrisonliew in #1451
• Always initialize fpga-shells with init-submodules.sh by @jerryz123 in #1456
• Support uni-directional TLSerdesser by @jerryz123 in #1476
• Move xcelium.mk out of top-level by @jerryz123 in #1482
• Set default config back to 1-channel by @jerryz123 in #1483
• Unify supernode/harness-clocking across chipyard/firesim/fpga by @jerryz123 in #1474
• Use fat jar's to remove SBT invocations by @abejgonzalez in #1375
• Bump to latest rocket-chip by @jerryz123 in #1475
• Improvements to chipyard clocking by @jerryz123 in #1489
• Downgrade cryptography | Pin linux sysroot by @abejgonzalez in #1494
• bump mempress by @joey0320 in #1498
• bump sha3 by @joey0320 in #1499
• Bump FireMarshal by @abejgonzalez in #1502
• Split NVDLA config out of ManyMMIOAccels config to reduce CI load by @jerryz123 in #1503
• Ignore barstools compilation if not needed by @abejgonzalez in #1504
• Disable NVDLA simulations in CI by @jerryz123 in #1507
• Update NoC example config to match new PRCI organization by @jerryz123 in #1509
• Bump gemmini by @jerryz123 in #1519

Fixed

• Various improvements and fixes by @jerryz123 in #1420
• Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in #1425
• Clear screen on prompt by @abejgonzalez in #1449
• misc: many fixes to cospike by @tianrui-wei in #1450
• Uniquify module names that are common to Top & Model by @joey0320 in #1442
• Use pk/encoding.h for hello/mt-hello by @jerryz123 in #1454
• Fix no-uart configs by @jerryz123 in #1457
• Fix support for no-bootROM systems by @jerryz123 in #1458
• Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies by @jerryz123 in #1460
• uniquify module names by @joey0320 in #1452
• Flip serial_tl_clock to be generated off-chip by @jerryz123 in #1445
• Move TestHarness to chipyard.harness, make chipyard/harness directory by @jerryz123 in #1463
• Separate out conda-lock generation into new script by @abejgonzalez in #1466
• Bump DRAMSim2 to avoid verbose log files by @jerryz123 in #1468
• Bump Verilator and use TestDriver.v as top by @abejgonzalez in #1398
• Add 1GB / 4GB DRAM firechip configs for FireSim VCU118 by @sagark in #1471
• Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness by @jerryz123 in #1465
• Make BootAddrReg optional by @jerryz123 in #1464
• Fix vcd/fst/fsdb waveform generation by @jerryz123 in #1473
• Switch RTL sims to absolute clock-generators by @jerryz123 in #1472
• Generate objdump | check BINARY | cospike fixes by @jerryz123 in #1467
• Small QOL fixes for Xcelium by @abejgonzalez in #1485
• (VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus by @jerryhethatday in #1487
• Force conda-lock to v1 by @abejgonzalez in #1492
• Loosen/tighten conda requirements | Fix conda-lock req by @abejgonzalez in #1497
• Misc Makefile Fixes by @abejgonzalez in #1496
• Bump constellation to fix interconnect FIFO-fixers by @jerryz123 in #1510
• [ci skip] Fix broken docs link by @jerryz123 in #1515
• Revert changes to peripheral fragments by @jerryz123 in #1518

New Contributors

• @tianrui-wei made their first contribution in #1450
• @jerryhethatday made their first contribution in #1487
• @nikhiljha made their first contribution in #1486