Bump to chisel 6 release

.github/workflows/test.yml

@@ -91,9 +91,10 @@ jobs:
         # 4.034: Chipyard
         # 4.038: Ubuntu 20.10
         # 4.108: Fedora 34
-        # 4.200: currently the latest version on brew (MacOS)
         # 4.202: added "forcePerInstance" to support our coverage flow
-        version: ["4.028", "4.032", "4.034", "4.038", "4.108", "4.200", "4.202"]
+        # 5.018: currently the latest version on brew (macOS)
+        # 5.020: latest release
+        version: ["4.028", "4.032", "4.034", "4.038", "4.108", "4.200", "4.202", "5.018", "5.020"]
 
     steps:
       - name: Checkout

build.sbt

@@ -2,20 +2,21 @@
 
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
-  scalaVersion := "2.13.10",
-  crossScalaVersions := Seq("2.13.10")
+  scalaVersion := "2.13.12",
+  crossScalaVersions := Seq("2.13.12")
 )
 
-val chiselVersion = "6.0.0-M3"
+val chiselVersion = "6.0.0"
 val firrtlVersion = "6.0-SNAPSHOT"
 
 lazy val chiseltestSettings = Seq(
   name := "chiseltest",
   // we keep in sync with chisel version names
-  version := "6.0-SNAPSHOT",
+  version := "6.0.0",
   scalacOptions := Seq(
     "-deprecation",
     "-feature",
+    "-Xcheckinit",
     "-language:reflectiveCalls",
     // do not warn about firrtl imports, once the firrtl repo is removed, we will need to import the code
     "-Wconf:cat=deprecation&msg=Importing from firrtl is deprecated:s",

project/build.properties

@@ -1 +1 @@
-sbt.version=1.8.2
+sbt.version=1.9.8

src/main/scala/chiseltest/iotesters/PeekPokeTester.scala

@@ -112,9 +112,9 @@ abstract class PeekPokeTester[T <: Module](val dut: T) extends LazyLogging {
   private def maskedBigInt(bigInt: BigInt, width: Int): BigInt = bigInt & ((BigInt(1) << width) - 1)
 
   // helps us work around the fact that signal.width is private!
-  private def getFirrtlWidth(signal: Bits): chisel3.internal.firrtl.Width = signal.widthOption match {
-    case Some(value) => chisel3.internal.firrtl.KnownWidth(value)
-    case None        => chisel3.internal.firrtl.UnknownWidth()
+  private def getFirrtlWidth(signal: Bits): chisel3.Width = signal.widthOption match {
+    case Some(value) => chisel3.KnownWidth(value)
+    case None        => chisel3.UnknownWidth()
   }
 
   /** Locate a specific bundle element, given a name path. TODO: Handle Vecs

src/main/scala/chiseltest/package.scala

@@ -324,9 +324,9 @@ package object chiseltest {
     }
 
     // helps us work around the fact that signal.width is private!
-    def getFirrtlWidth(signal: Bits): chisel3.internal.firrtl.Width = signal.widthOption match {
-      case Some(value) => chisel3.internal.firrtl.KnownWidth(value)
-      case None        => chisel3.internal.firrtl.UnknownWidth()
+    def getFirrtlWidth(signal: Bits): chisel3.Width = signal.widthOption match {
+      case Some(value) => chisel3.KnownWidth(value)
+      case None        => chisel3.UnknownWidth()
     }
 
     def boolBitsToString(bits: BigInt): String = (bits != 0).toString

src/main/scala/chiseltest/simulator/ChiselBridge.scala

@@ -154,7 +154,8 @@ private object ChiselBridge {
     // ignoreDecodeTableAnnotation since it is not needed by the firrtl compiler
     case _: DecodeTableAnnotation => None
     //
-    case _ => throw new NotImplementedError(s"TODO: convert ${anno}")
+    case _ => Some(UnsupportedAnnotation(anno.getClass.getSimpleName, anno.toString))
+    // case _ => throw new NotImplementedError(s"TODO: convert ${anno}")
   }
 
   private def convert(c: Circuit): firrtl2.ir.Circuit =

src/main/scala/chiseltest/simulator/VerilatorCoverage.scala

@@ -32,12 +32,13 @@ private object VerilatorCoverage {
     Coverage.collectCoverageAnnotations(annos) ++ annos.collect { case a: OrderedCoverPointsAnnotation => a }
   }
 
-  def loadCoverage(annos: AnnotationSeq, coverageData: os.Path): List[(String, Long)] = {
+  def loadCoverage(annos: AnnotationSeq, coverageData: os.Path, version: (Int, Int)): List[(String, Long)] = {
     val entries = parseCoverageData(coverageData)
-    verilatorCoverageToCoverageMap(entries, annos)
+    verilatorCoverageToCoverageMap(entries, annos, version)
   }
 
-  private def verilatorCoverageToCoverageMap(es: List[CoverageEntry], annos: AnnotationSeq): List[(String, Long)] = {
+  private def verilatorCoverageToCoverageMap(es: List[CoverageEntry], annos: AnnotationSeq, version: (Int, Int))
+    : List[(String, Long)] = {
     // map from module name to an ordered list of cover points in said module
     val coverPoints = annos.collect { case a: OrderedCoverPointsAnnotation => a.target.module -> a.covers }.toMap
     // map from instance path name to the name of the module
@@ -49,8 +50,19 @@ private object VerilatorCoverage {
     // process the coverage entries on a per instance basis
     es.groupBy(_.path).toList.flatMap { case (name, entries) =>
       // we look up the cover points by first converting to the module name
-      val covers = coverPoints(instToModule(name))
-      processInstanceCoverage(name, covers, entries)
+      instToModule.get(name) match {
+        case Some(module) =>
+          val covers = coverPoints(module)
+          processInstanceCoverage(name, covers, entries)
+        case None if name.contains("*") =>
+          instToModule.flatMap {
+            case (inst, module) if inst.matches(name.replace("*", ".*")) =>
+              val covers = coverPoints(module)
+              processInstanceCoverage(inst, covers, entries)
+            case _ => Nil
+          }
+        case _ => throw new RuntimeException(s"Could not find module for instance: $name")
+      }
     }
   }
 

src/main/scala/chiseltest/simulator/VerilatorSimulator.scala

@@ -105,7 +105,7 @@ private object VerilatorSimulator extends Simulator {
     val coverageFile = targetDir / "coverage.dat"
     def readCoverage(): List[(String, Long)] = {
       assert(os.exists(coverageFile), s"Could not find `$coverageFile` file!")
-      VerilatorCoverage.loadCoverage(coverageAnnos, coverageFile)
+      VerilatorCoverage.loadCoverage(coverageAnnos, coverageFile, (majorVersion, minorVersion))
     }
 
     val args = getSimulatorArgs(state)
@@ -152,7 +152,7 @@ private object VerilatorSimulator extends Simulator {
     val coverageFile = targetDir / "coverage.dat"
     def readCoverage(): List[(String, Long)] = {
       assert(os.exists(coverageFile), s"Could not find `$coverageFile` file!")
-      VerilatorCoverage.loadCoverage(coverageAnnos, coverageFile)
+      VerilatorCoverage.loadCoverage(coverageAnnos, coverageFile, (majorVersion, minorVersion))
     }
 
     val args = getSimulatorArgs(state)

src/main/scala/treadle2/stage/phases/GetFirrtlAst.scala

@@ -38,7 +38,7 @@ object GetFirrtlAst extends Phase {
     def handleFirrtlFile(): Option[AnnotationSeq] = {
       annotationSeq.collectFirst { case FirrtlFileAnnotation(fileName) => fileName } match {
         case Some(fileName) =>
-          val file = io.Source.fromFile(fileName)
+          val file = scala.io.Source.fromFile(fileName)
           val text = file.mkString
           file.close()
 

src/test/scala/chiseltest/simulator/Verilator.scala

@@ -28,7 +28,7 @@ class VerilatorSpecificTests extends FlatSpecWithTargetDir {
     val (_, out) = CaptureStdout {
       sim.findVersions()
     }
-    assert(out.contains("Found Verilator 4"))
+    assert(out.contains("Found Verilator "))
   }
 
   it should "print out commands and verilator results in debug mode" taggedAs RequiresVerilator in {
@@ -45,8 +45,6 @@ class VerilatorSpecificTests extends FlatSpecWithTargetDir {
     val verilatorBinName = if (JNAUtils.isWindows) { "verilator_bin" }
     else { "verilator" }
     assert(out.contains(s"${verilatorBinName} --cc --exe "))
-    assert(out.contains("g++"))
-    assert(out.contains("perl"))
     assert(out.contains("make -C"))
   }
 }

src/test/scala/chiseltest/tests/VecPokeExpectTest.scala

@@ -8,7 +8,7 @@ import org.scalatest.freespec.AnyFreeSpec
 
 class UsesVec extends Module {
   val in = IO(Input(Vec(4, UInt(5.W))))
-  val addr = IO(Input(UInt(8.W)))
+  val addr = IO(Input(UInt(2.W)))
   val out = IO(Output(UInt(5.W)))
 
   out := in(addr)

src/test/scala/treadle2/ModuleInLineSpec.scala

@@ -12,7 +12,7 @@ class ModuleInLineSpec extends AnyFlatSpec with Matchers with LazyLogging {
 
   it should "expand instances as found" in {
     val stream = getClass.getResourceAsStream("/treadle/three_deep.fir")
-    val input = io.Source.fromInputStream(stream).mkString
+    val input = scala.io.Source.fromInputStream(stream).mkString
 
     TreadleTestHarness(Seq(FirrtlSourceAnnotation(input))) { tester =>
       tester.engine.symbolTable.outputPortsNames.size should be > 0
@@ -21,7 +21,7 @@ class ModuleInLineSpec extends AnyFlatSpec with Matchers with LazyLogging {
 
   it should "nester registers should all be using the same clock" in {
     val stream = getClass.getResourceAsStream("/treadle/NestedModsWithReg.fir")
-    val input = io.Source.fromInputStream(stream).mkString
+    val input = scala.io.Source.fromInputStream(stream).mkString
 
     TreadleTestHarness(Seq(FirrtlSourceAnnotation(input))) { tester =>
       def testIt(): Unit = {