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SystemVerilog: refactoring changes #2664
SystemVerilog: refactoring changes #2664
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reorder case statements
readWordToken(): clear token->name only when it read a word token. simplify the calculation of the return value
process*() can use "token" object freely by this fix.
instead of K_UNDEFINED for an identifier token This makes the intension of source code more clear.
Codecov Report
@@ Coverage Diff @@
## master #2664 +/- ##
==========================================
+ Coverage 86.90% 86.91% +0.01%
==========================================
Files 183 183
Lines 39016 39014 -2
==========================================
+ Hits 33906 33909 +3
+ Misses 5110 5105 -5
Continue to review full report at Codecov.
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{ | ||
tagEntryInfo tag; | ||
verilogKind kind; | ||
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(This is not a must.)
How about putting "Assert (kind >= 0);" here?
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Good point!
I left the following comment.
On some condition these lines are executed. I cannot assert here.
I need some more code clean-up.
/* FIXME: This if-clause should be removed. */
if (kind == K_UNDEFINED || kind == K_IDENTIFIER)
{
verbose ("Unexpected token kind %d\n", kind);
return;
}
LGTM. |
You use verbose in some places. It is o.k. but I would like to introduce trace.h as an alterantive. Macros defined in main/trace.h are useful. In many situations, they are better than verbose.
The macros are developed for new C/C++ parsers.
ENTER/LEAVE macros adjust the depth of indentation well. This is nothing to do with my reviewing for this pull request. Just for your information. |
Double quotes are handled by skipWhite().
test code for procedural programming statements
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Thank you. I will study trace.h. It looks good. After checking the coverage report, I made a fix on skipExpression() and I added test code.
May I commit this? |
Yes. |
Thank you for your review. |
I did not merged this pull request. |
Before making fixes for known issues I made several refactoring changes.
See comment on each commit. The number of line of change is large, but each of them is simple change.
make units LANGUAGES=SystemVerilog,Verilog VG=1
passed.