Verilog/SystemVerilog Parser TODO List

[hirooih]

Here is a TODO list of Verilog/SystemVerilog parser. It is ordered in priority, from higher to lower.

If you find any other missing issues or requests to raise priority, please leave your comment on this issue ticket.
Your feedback helps other users and us.

Known Bugs

• isIdentifierCharacter() does not handle '$` properly SystemVerilog: handle an identifier include '$' #2680
• preprocessor directive related issues SystemVerilog: improve compiler directive support #2675
  • `else in port lists
  • multi-line macro definition
• update descriptions of kinds SystemVerilog: several kind related fixes #2684
• skip paired parens and braces in the main loop
• a void function is tagged as instance (cf. verilog: keep trace with instance in TAGS file #2703)
• fixme in systemverilog-net-var.d/inputs.sv SystemVerilog: introduce processType() for consistent type-handling #2696, SystemVerilog: Misc Fixes #2750
  • typedef p.data_t my_data_t; SystemVerilog: port list fix and others #2753
• fixme in systemverilog-module.d/inputs.sv
  • no direction on the first port of module SystemVerilog: port list fix and others #2753
• fixme in systemverilog-parameter.d/inputs.sv
  • interface class (LRM 8.26) SystemVerilog: implement unsupported features in processDesignElement() #2737
  • suppress parameter field in generate block (cf. (System-)Verilog: Parameters/Localparams/Specparams should be seperated #2537)
• fixme in systemverilog-task-function.d/inputs.sv
  • function void foo::bar(); SystemVerilog: Parsing error when the subroutine's return type contains class resolution :: #4109, Verilog: Fix function parse when return type contains :: #4111
  • function foo #(IF) bar(); SystemVerilog: Parsing error when the subroutine's return type contains class resolution :: #4109, Verilog: Fix function parse when return type contains :: #4111
• user defined type on enum -> generic type handling SystemVerilog: introduce processType() for consistent type-handling #2696

Features Not Implemented Yet

• tag module and interface instance name verilog: keep trace with instance in TAGS file #2703
• clocking-clockingend, checker-endchecker SystemVerilog: several kind related fixes #2684
• members in structures (cf. SystemVerilog: introduce processType() for consistent type-handling #2696) SystemVerilog: support struct and union member #2701
• tag nettype SystemVerilog: Misc Fixes #2750
• tag constraint SystemVerilog: Misc Fixes #2750
• covergroup SystemVerilog: implement unsupported features in processDesignElement() #2737
• import as prototype (ignore as pure and context) SystemVerilog: implement unsupported features in processDesignElement() #2737
• interface class (LRM 8.26) SystemVerilog: implement unsupported features in processDesignElement() #2737
• life_time in class declaration SystemVerilog: Misc Fixes #2750
• array manipulation methods (foo.sort()) SystemVerilog: Misc Fixes #2750
• class_type with parameter_value_assignment (foo#(a)::bar)
• element range on enum
• new fields
  • implement field for interface class
  • typeref field for instances (cf. verilog: keep trace with instance in TAGS file #2703)
  • type information like C parser (cf. SystemVerilog: introduce processType() for consistent type-handling #2696)
  • macrodef and signature field support (cf. SystemVerilog: improve compiler directive support #2675)
• escaped identifiers (LRM 5.6.1)

Refactoring

• simplify token handling SystemVerilog: handle an identifier include '$' #2680
• divide processDesignElement() SystemVerilog: implement unsupported features in processDesignElement() #2737
• apply skipExpresson() on processPortList() SystemVerilog: introduce processType() for consistent type-handling #2696
• unify processPortList() and tagNameList() SystemVerilog: introduce processType() for consistent type-handling #2696
  • refactor skipMacro() called by only processPortList() and tagNameList()
• introduce skipType() (generic type handling) SystemVerilog: introduce processType() for consistent type-handling #2696
• consistent input character handling SystemVerilog,refactor: consistent input character handling #2721
• call updateKind() in readWordToken() SystemVerilog: refactor readWordToken() #2722
• use trace.h

NOTE

• Please, read ctags(1) and understand the fundamental concepts in ctags including the definition tags, reference tags, kinds, fields, extras, and pseudo-tags before commenting.
• If possible, take a look at parsers/verilog.c before adding something.
• @hirooih will update, delete, or edit your comments for keeping this as our TODO list.