SystemVerilog,refactor: consistent input character handling #2721

hirooih · 2020-11-22T14:50:58Z

This fix makes input character handling consistent.
Until now, character input processing has been executed in an ad hoc way.

Each function which executes character input has argument "c" and returns "c".
It calls skipWhite() before return.

Argument c of process*() points the first charactor of the next token. "skipWhite (vGetc ())" is done findVerilogTags().

systemverilog-net-var.d/input.sv: comment out nettype test which is not supported yet

coveralls · 2020-11-22T14:55:02Z

Coverage decreased (-0.002%) to 87.085% when pulling 61530bb on hirooih:sv-char-handling into bdeb61a on universal-ctags:master.

codecov · 2020-11-22T15:00:38Z

Codecov Report

Merging #2721 (61530bb) into master (bdeb61a) will increase coverage by 0.00%.
The diff coverage is 97.59%.

@@           Coverage Diff           @@
##           master    #2721   +/-   ##
=======================================
  Coverage   86.99%   87.00%           
=======================================
  Files         185      185           
  Lines       39465    39480   +15     
=======================================
+ Hits        34334    34348   +14     
- Misses       5131     5132    +1

Impacted Files	Coverage Δ
parsers/verilog.c	`98.62% <97.59%> (-0.13%)`	⬇️

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hirooih · 2020-11-22T15:16:49Z

This is the first half of a big refactoring.

@masatake san, this pull-request is 5 steps of refactoring changes but it changed basic way of input character handling.
Please review it.

Coverage is decreased due to sanity check. So it is OK.

masatake · 2020-11-23T01:57:35Z

Units/parser-verilog.r/systemverilog-net-var.d/input.sv

@@ -50,7 +50,7 @@ module Net_declarations;

  // 6.7.2 Net declarations with user-defined nettypes
  nettype T wT;
-  nettype T wTsum with Tsum;  // FIXME: 
+  //nettype T wTsum with Tsum;  // FIXME: "nettype" and "with" are unsupported


This is o.k.

FYI
.b test can be a tool for recording this kind of situation.
https://docs.ctags.io/en/latest/units.html#gathering-test-cases-for-known-bugs

hirooih added 5 commits November 22, 2020 23:35

SystemVerilog,refactor: processParameterList() returns "c"

f3d6010

SystemVerilog,refactor: refactor findBlockName() to skipBlockName()

91b5c3f

SystemVerilog,refactor: add argument "c" on process*()

edc75f8

Argument c of process*() points the first charactor of the next token. "skipWhite (vGetc ())" is done findVerilogTags().

SystemVerilog,refactor: process*() return "c"

336b0d0

SystemVerilog,refactor: findTag() returns "c"

61530bb

systemverilog-net-var.d/input.sv: comment out nettype test which is not supported yet

hirooih requested a review from masatake November 22, 2020 15:08

hirooih mentioned this pull request Nov 23, 2020

Verilog/SystemVerilog Parser TODO List #2674

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masatake reviewed Nov 23, 2020

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masatake approved these changes Nov 23, 2020

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hirooih merged commit b56a34f into universal-ctags:master Nov 23, 2020

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SystemVerilog,refactor: consistent input character handling #2721

SystemVerilog,refactor: consistent input character handling #2721

hirooih commented Nov 22, 2020

coveralls commented Nov 22, 2020

codecov bot commented Nov 22, 2020 •

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hirooih commented Nov 22, 2020

masatake Nov 23, 2020

hirooih Nov 23, 2020

SystemVerilog,refactor: consistent input character handling #2721

SystemVerilog,refactor: consistent input character handling #2721

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hirooih commented Nov 22, 2020

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codecov bot commented Nov 22, 2020 • edited Loading

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hirooih commented Nov 22, 2020

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codecov bot commented Nov 22, 2020 •

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