SystemVerilog: port list fix and others

[hirooih]

• fix module port tagging bugs
  • net type and user-defined type ports are tagged as port.
  • correctly distinguishes between ANSI port and non-ANSI port.
  • merge with processPortList()
• define swapToken() for K_WITH handling (proposed by @masatake san)
• fixes for uncovered lines

All high-priority items are implemented by this pull-request.

[coveralls]

Coverage increased (+0.03%) to 87.165% when pulling 1f209b7 on hirooih:sv-port-list into 69df9dc on universal-ctags:master.

[codecov]

Codecov Report

Merging #2753 (1f209b7) into master (bdb7d99) will increase coverage by 0.08%.
The diff coverage is 100.00%.

@@            Coverage Diff             @@
##           master    #2753      +/-   ##
==========================================
+ Coverage   86.99%   87.08%   +0.08%     
==========================================
  Files         190      191       +1     
  Lines       40496    40784     +288     
==========================================
+ Hits        35230    35517     +287     
- Misses       5266     5267       +1     

Impacted Files	Coverage Δ
parsers/verilog.c	98.24% <100.00%> (+1.27%)	⬆️
main/field.c	95.67% <0.00%> (-0.19%)	⬇️
parsers/haskell.c	91.12% <0.00%> (ø)
main/writer-ctags.c	98.70% <0.00%> (+<0.01%)	⬆️
main/read.c	96.19% <0.00%> (+0.05%)	⬆️
main/routines.c	81.18% <0.00%> (+0.06%)	⬆️
main/entry.c	88.83% <0.00%> (+0.46%)	⬆️
parsers/vhdl.c	96.26% <0.00%> (+0.86%)	⬆️
main/vstring.c	91.95% <0.00%> (+1.72%)	⬆️

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[hirooih]

I've removed some more uncovered lines.