[WIP] Synlig, new system-verilog tool integration #2841
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amirarjmand93
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@vaughnbetz This branch is working on the local pc fine without any problem. but in the CI test, I am getting some errors related to JAVA dependency while making files. for Synlig we need some packages to be installed:
I tried to append some packages from this list that are missing from our flow. (like
This error arises from most of the ci tests: |
amirarjmand93
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@AlexandreSinger @soheilshahrouz : any ideas? |
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amirarjmand93
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why hasn't the nightly test been launched? |
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We had to turn off automatic launch of the nightly tests as we don't have the google cloud going. You should run some or all of the nightly tests manually if this code change could break them. @AlexandreSinger : not sure if you have a button that can launch the nightly tests on one of our SAVI servers or not yet. |
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1- vtr_reg_system_verilog.log.txt The two tests from the nightly tests related to SystemVerilog were run successfully with Synlig enabled(
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It seems like you have 3 copies of the make_sv_flattened.py script. Why not put it in the base f4pga directory instead and just call it from there (with ../../make_sv_flattened.py)? Or put it in the search path.
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| # Separate opt for Parmys execution(verilog or system-verilog) | ||
| if {$env(PARSER) == "default"} { | ||
| puts "Running Parmys with disables additional passes " |
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I'm not sure what this output means. Do you mean to say "Running parmys with no additional passes." ?
| parmys -a QQQ -nopass -c CCC YYY | ||
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| } elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} { | ||
| puts "Running Parmys with Additional Passes Resolve Conflicts" |
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I'm not sure what this output means. Wouldn't it be more clear to say "Running Parmys with additional passes to flatten all files and parse SystemVerilog" ?
| @@ -65,9 +65,9 @@ jobs: | |||
| - {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"} | |||
| - {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} | |||
| - {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} | |||
| # - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42) | |||
| - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42) | |||
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The comment looks out of date -- it says this test is turned off, but you are turning it back on. Delete the comment.
Also is synlig part of f4pga_plugins? If not, it would be better to change the name of the cmake variable to synlig for clarity.
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I am aware of these comments and duplicates. I just want to ensure that we are technically finished with this update and the last commits. I will make the minor changes and let you know. |
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