[WIP] Synlig, new system-verilog tool integration

.github/workflows/nightly_test.yml

@@ -65,9 +65,9 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          # - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
+          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=OFF",                                     extra_pkgs: ""}
+          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"

.gitpod.Dockerfile

@@ -30,6 +30,7 @@ RUN apt-get update \
   python-lxml \
   qt5-default \
   wget \
+  default-jre \
   && apt-get clean \
   && rm -rf /var/lib/apt/lists/*
 

Dockerfile

@@ -15,6 +15,7 @@ RUN apt-get update -qq \
     && apt-get -y install --no-install-recommends \
     wget \
     ninja-build \
+    default-jre \
     libeigen3-dev \
     libtbb-dev \
     python3-pip \

install_apt_packages.sh

@@ -34,6 +34,7 @@ sudo apt-get install -y \
     libboost-system-dev \
     libboost-python-dev \
     libboost-filesystem-dev \
+    default-jre \
     zlib1g-dev
 
 # Required to build the documentation

libs/EXTERNAL/CMakeLists.txt

@@ -1,4 +1,5 @@
 include(ExternalProject)
+include(ProcessorCount)
 
 #Manually synchronized external libraries
 add_subdirectory(libpugixml)
@@ -9,8 +10,17 @@ add_subdirectory(libsdcparse)
 add_subdirectory(libblifparse)
 add_subdirectory(libtatum)
 add_subdirectory(libcatch2)
+#add_subdirectory(synlig)
 #add_subdirectory(parmys)
 
+#Proc numbers
+ProcessorCount(PROCESSOR_COUNT)
+
+if(PROCESSOR_COUNT EQUAL 0)
+    # Fallback to 1 if the processor count cannot be determined
+    set(PROCESSOR_COUNT 1)
+endif()
+
 #VPR_USE_SERVER is initialized in the root CMakeLists
 #compile sockpp only if server mode is enabled
 if (VPR_USE_SERVER)
@@ -27,8 +37,9 @@ endif ()
 
 # The VTR root CMakeFile initializes the WITH_PARMYS
 if (${WITH_PARMYS})
-    # building Surelog and UHDM in a custom target to avoid any target conflict with VTR targets
+
     if (${YOSYS_F4PGA_PLUGINS})
+
         set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
         set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build)
         set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins)
@@ -62,74 +73,90 @@ if (${WITH_PARMYS})
                 LOG_OUTPUT_ON_FAILURE ON
 
                 # dependency
-                DEPENDS yosys
+                DEPENDS  yosys
                 )
 
-        ExternalProject_Add(f4pga-plugins
-                # root directory for the Yosys-F4PGA-Plugins project
-                PREFIX "f4pga-plugins"
-
-                GIT_REPOSITORY https://github.com/chipsalliance/yosys-f4pga-plugins.git
-                GIT_TAG v1.20230808
-                GIT_PROGRESS TRUE
-                GIT_SHALLOW TRUE
-
-                # setting source, build and install directories
-                SOURCE_DIR "${YOSYS_F4PGA_PLUGINS_SOURCE_DIR}"
-                BUILD_IN_SOURCE FALSE
-                INSTALL_DIR ""
-
-                INSTALL_COMMAND ""
-                CONFIGURE_COMMAND ""
-                BUILD_COMMAND ${MAKE_PROGRAM} -C ${YOSYS_F4PGA_PLUGINS_SOURCE_DIR}
-                PATH=${CMAKE_BINARY_DIR}/bin/:$ENV{PATH}
-                UHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}
-                BUILD_DIR=${CMAKE_CURRENT_BINARY_DIR}/f4pga-plugins/$(NAME) # NAME will be resolved by yosys-f4pga-plugins Make
-                YOSYS_PATH=${CMAKE_BINARY_DIR}
-                install -j${CUSTOM_BUILD_PARALLEL_LEVEL}
-
-                # redirect logs to a logfile
-                LOG_BUILD ON
-                LOG_UPDATE ON
-                LOG_INSTALL ON
-                LOG_CONFIGURE OFF
-                LOG_OUTPUT_ON_FAILURE ON
+     # Synlig integration (manages Surelog and UHDM internally)                
+
+        # Synlig integration (manages Surelog and UHDM internally)
+        set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig)
+
+        # Clone Synlig repository and ensure submodules are synced before building
+        ExternalProject_Add(synlig
+            PREFIX "synlig"
+
+            # Clone the Synlig repository
+            GIT_REPOSITORY https://github.com/chipsalliance/synlig.git
+            GIT_TAG main
+            GIT_PROGRESS TRUE
+            GIT_SHALLOW TRUE
+
+            # Set source and build directories
+            SOURCE_DIR "${SYNLIG_SOURCE_DIR}"
+            BUILD_IN_SOURCE FALSE
+            INSTALL_DIR " "
+
+            # Sync submodules after cloning
+
+
+            UPDATE_COMMAND git submodule update --init --recursive third_party/surelog
+            WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR}
+
+            BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT}
+            INSTALL_COMMAND ""
+            CONFIGURE_COMMAND ""
+
+            # Pass necessary paths and set environment variables
+            CMAKE_CACHE_ARGS
+                "-DCMAKE_BUILD_TYPE:STRING=Release"
+                "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog"
+                "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys"
+                "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}"
+                "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build"
+                "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}"
+
+            LOG_BUILD ON
+            LOG_UPDATE ON
+            LOG_INSTALL ON
+            LOG_CONFIGURE OFF
+            LOG_OUTPUT_ON_FAILURE ON
+
+            # Ensure dependencies like Yosys are built first
+            DEPENDS yosys  # Ensure submodule sync runs before synlig build
+        )
 
-                # dependency
-                DEPENDS surelog yosys
-                )
     endif ()
-
 endif ()
 
-if (${VTR_ENABLE_CAPNPROTO})
-    # Override default policy for capnproto (CMake policy version 3.1)
-    # Enable new IPO variables
-    set(CMAKE_POLICY_DEFAULT_CMP0069 NEW)
 
-    # Enable option overrides via variables
-    set(CMAKE_POLICY_DEFAULT_CMP0077 NEW)
+    if (${VTR_ENABLE_CAPNPROTO})
+        # Override default policy for capnproto (CMake policy version 3.1)
+        # Enable new IPO variables
+        set(CMAKE_POLICY_DEFAULT_CMP0069 NEW)
 
-    # Re-enable CXX extensions for capnproto.
-    set(CMAKE_CXX_EXTENSIONS ON)
+        # Enable option overrides via variables
+        set(CMAKE_POLICY_DEFAULT_CMP0077 NEW)
 
-    # Disable capnproto tests
-    set(BUILD_TESTING OFF)
+        # Re-enable CXX extensions for capnproto.
+        set(CMAKE_CXX_EXTENSIONS ON)
 
-    #Since capnproto is an externally developed library/tool, we suppress all compiler warnings
-    CHECK_CXX_COMPILER_FLAG("-w" CXX_COMPILER_SUPPORTS_-w)
-    if (CXX_COMPILER_SUPPORTS_-w)
-        add_compile_options("-w")
-    endif ()
+        # Disable capnproto tests
+        set(BUILD_TESTING OFF)
 
-    add_subdirectory(capnproto EXCLUDE_FROM_ALL)
+        #Since capnproto is an externally developed library/tool, we suppress all compiler warnings
+        CHECK_CXX_COMPILER_FLAG("-w" CXX_COMPILER_SUPPORTS_-w)
+        if (CXX_COMPILER_SUPPORTS_-w)
+            add_compile_options("-w")
+        endif ()
 
-    #Some capnproto kj headers (e.g. filesystem.h) generate warnings, treat them as system headers to suppress warnings
-    #We suppress them here since we include the capnproto sub-tree as is and do not modify its CMakeLists.txts
-    target_include_directories(kj SYSTEM INTERFACE
-            $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/capnproto/c++/src>
-            $<INSTALL_INTERFACE:include>
-            )
+        add_subdirectory(capnproto EXCLUDE_FROM_ALL)
+
+        #Some capnproto kj headers (e.g. filesystem.h) generate warnings, treat them as system headers to suppress warnings
+        #We suppress them here since we include the capnproto sub-tree as is and do not modify its CMakeLists.txts
+        target_include_directories(kj SYSTEM INTERFACE
+                $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/capnproto/c++/src>
+                $<INSTALL_INTERFACE:include>
+                )
 endif ()
 
 # Some catch2 headers generate warnings, so treat them as system headers to suppress warnings

vtr_flow/benchmarks/system_verilog/f4pga/README.md

@@ -4,4 +4,14 @@ This folder contains the `button_controller`, `pulse_width_led` and `timer` benc
 The benchmarks are directly copied to avoid dealing with a significant amount of code by adding the F4PGA repository as a subtree to the VTR repository.
 The primary purpose of these benchmarks is to utilize them in VTR GitHub CI tests to continuously monitor the functionality of the Yosys SystemVerilog and UHDM plugins.
 
-For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository.
+For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository.
+
+## SystemVerilog File Flattening with `make_sv_flattened.py`
+
+The current SystemVerilog tool, **Synlig**, cannot process multiple files as input (e.g., a top module and its dependencies). To address this limitation, use the script `make_sv_flattened.py` to flatten the files into a single SystemVerilog file. This will convert any design with dependencies into one flattened SystemVerilog file, ensuring compatibility with Synlig.
+
+### Instructions:
+1. Ensure the `make_sv_flattened.py` script is located in the folder where your SystemVerilog files (e.g., the top module and its dependencies) are gathered.
+2. Run the `make_sv_flattened.py` script on the gathered files in that folder.
+3. The script will output a single flattened SystemVerilog file, ready for use with Synlig.
+