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dialects: (riscv) fix signedness in riscv #2100

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Feb 6, 2024
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dialects: (riscv) fix signedness in riscv #2100

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b9b41a6
dialects: (builtin)
superlopuh Feb 6, 2024
405043f
dialects: (riscv) Li value has 20 bits
superlopuh Feb 6, 2024
e362b91
fix bitwidth in riscv
superlopuh Feb 6, 2024
6cbf8ac
dialects: (riscv) fix signedness in riscv
superlopuh Feb 6, 2024
b627a0c
i12
superlopuh Feb 6, 2024
5942103
fix tests
superlopuh Feb 6, 2024
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42 changes: 27 additions & 15 deletions tests/dialects/test_riscv.py
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
import pytest

from xdsl.dialects import riscv
from xdsl.dialects.builtin import IntegerAttr, ModuleOp, i32
from xdsl.dialects.builtin import IntegerAttr, ModuleOp, Signedness, i32
from xdsl.ir import MLContext
from xdsl.parser import Parser
from xdsl.utils.exceptions import ParseError, VerifyException
Expand Down Expand Up @@ -121,42 +121,49 @@ def test_return_op():

def test_immediate_i_inst():
# I-Type - 12-bits immediate
lb, ub = Signedness.SIGNLESS.value_range(12)
a1 = TestSSAValue(riscv.Registers.A1)

with pytest.raises(VerifyException):
riscv.AddiOp(a1, 1 << 11, rd=riscv.Registers.A0)
riscv.AddiOp(a1, ub, rd=riscv.Registers.A0)

with pytest.raises(VerifyException):
riscv.AddiOp(a1, -(1 << 11) - 2, rd=riscv.Registers.A0)
riscv.AddiOp(a1, lb - 1, rd=riscv.Registers.A0)

riscv.AddiOp(a1, -(1 << 11), rd=riscv.Registers.A0)
riscv.AddiOp(a1, (1 << 11) - 1, rd=riscv.Registers.A0)
riscv.AddiOp(a1, ub - 1, rd=riscv.Registers.A0)
riscv.AddiOp(a1, lb, rd=riscv.Registers.A0)


def test_immediate_s_inst():
# S-Type - 12-bits immediate
lb, ub = Signedness.SIGNLESS.value_range(12)
a1 = TestSSAValue(riscv.Registers.A1)
a2 = TestSSAValue(riscv.Registers.A2)

with pytest.raises(VerifyException):
riscv.SwOp(a1, a2, 1 << 11)
riscv.SwOp(a1, a2, ub)

with pytest.raises(VerifyException):
riscv.SwOp(a1, a2, -(1 << 11) - 2)
riscv.SwOp(a1, a2, lb - 1)

riscv.SwOp(a1, a2, -(1 << 11))
riscv.SwOp(a1, a2, (1 << 11) - 1)
riscv.SwOp(a1, a2, ub - 1)
riscv.SwOp(a1, a2, lb)


def test_immediate_u_j_inst():
# U-Type and J-Type - 20-bits immediate
lb, ub = Signedness.SIGNLESS.value_range(20)
assert ub == 1048576
assert lb == -524288

with pytest.raises(VerifyException):
riscv.LuiOp(1 << 20)
riscv.LuiOp(ub)

with pytest.raises(VerifyException):
riscv.LuiOp(-(1 << 20) - 2)
riscv.LuiOp(lb - 1)

riscv.LuiOp((1 << 20) - 1)
riscv.LuiOp(ub - 1)
riscv.LuiOp(lb)


def test_immediate_jalr_inst():
Expand All @@ -173,14 +180,19 @@ def test_immediate_jalr_inst():


def test_immediate_pseudo_inst():
lb, ub = Signedness.SIGNLESS.value_range(32)
assert ub == 4294967296
assert lb == -2147483648

# Pseudo-Instruction with custom handling
with pytest.raises(VerifyException):
riscv.LiOp(-(1 << 31) - 1, rd=riscv.Registers.A0)
riscv.LiOp(ub, rd=riscv.Registers.A0)

with pytest.raises(VerifyException):
riscv.LiOp(1 << 32, rd=riscv.Registers.A0)
riscv.LiOp(lb - 1, rd=riscv.Registers.A0)

riscv.LiOp((1 << 31) - 1, rd=riscv.Registers.A0)
riscv.LiOp(ub - 1, rd=riscv.Registers.A0)
riscv.LiOp(lb, rd=riscv.Registers.A0)


def test_immediate_shift_inst():
Expand Down
46 changes: 23 additions & 23 deletions tests/filecheck/dialects/riscv/riscv_ops.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -350,17 +350,17 @@
// CHECK-GENERIC-NEXT: "riscv_func.func"() ({
// CHECK-GENERIC-NEXT: %0 = "riscv.get_register"() : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %1 = "riscv.get_register"() : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %addi = "riscv.addi"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %slti = "riscv.slti"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %sltiu = "riscv.sltiu"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %andi = "riscv.andi"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %ori = "riscv.ori"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %xori = "riscv.xori"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %addi = "riscv.addi"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %slti = "riscv.slti"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %sltiu = "riscv.sltiu"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %andi = "riscv.andi"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %ori = "riscv.ori"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %xori = "riscv.xori"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %slli = "riscv.slli"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %srli = "riscv.srli"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %srai = "riscv.srai"(%0) {"immediate" = 1 : ui5} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lui = "riscv.lui"() {"immediate" = 1 : ui20} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %auipc = "riscv.auipc"() {"immediate" = 1 : ui20} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lui = "riscv.lui"() {"immediate" = 1 : i20} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %auipc = "riscv.auipc"() {"immediate" = 1 : i20} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %mv = "riscv.mv"(%0) : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %add = "riscv.add"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %slt = "riscv.slt"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
Expand Down Expand Up @@ -389,14 +389,14 @@
// CHECK-GENERIC-NEXT: "riscv.bge"(%0, %1) {"offset" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: "riscv.bltu"(%0, %1) {"offset" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: "riscv.bgeu"(%0, %1) {"offset" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: %lb = "riscv.lb"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lbu = "riscv.lbu"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lh = "riscv.lh"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lhu = "riscv.lhu"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lw = "riscv.lw"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: "riscv.sb"(%0, %1) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: "riscv.sh"(%0, %1) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: "riscv.sw"(%0, %1) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: %lb = "riscv.lb"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lbu = "riscv.lbu"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lh = "riscv.lh"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lhu = "riscv.lhu"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %lw = "riscv.lw"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: "riscv.sb"(%0, %1) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: "riscv.sh"(%0, %1) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: "riscv.sw"(%0, %1) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.reg<>) -> ()
// CHECK-GENERIC-NEXT: %csrrw_rw = "riscv.csrrw"(%0) {"csr" = 1024 : i32} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %csrrw_w = "riscv.csrrw"(%0) {"csr" = 1024 : i32, "writeonly"} : (!riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %csrrs_rw = "riscv.csrrs"(%0) {"csr" = 1024 : i32} : (!riscv.reg<>) -> !riscv.reg<>
Expand All @@ -418,16 +418,16 @@
// CHECK-GENERIC-NEXT: %divu = "riscv.divu"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %rem = "riscv.rem"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %remu = "riscv.remu"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %li = "riscv.li"() {"immediate" = 1 : si32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %li = "riscv.li"() {"immediate" = 1 : i32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: "riscv.ecall"() : () -> ()
// CHECK-GENERIC-NEXT: "riscv.ebreak"() : () -> ()
// CHECK-GENERIC-NEXT: "riscv.directive"() {"directive" = ".bss"} : () -> ()
// CHECK-GENERIC-NEXT: "riscv.directive"() {"directive" = ".align", "value" = "2"} : () -> ()
// CHECK-GENERIC-NEXT: "riscv.assembly_section"() ({
// CHECK-GENERIC-NEXT: %nested_li = "riscv.li"() {"immediate" = 1 : si32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %nested_li = "riscv.li"() {"immediate" = 1 : i32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: }) {"directive" = ".text", "foo" = i32} : () -> ()
// CHECK-GENERIC-NEXT: "riscv.assembly_section"() ({
// CHECK-GENERIC-NEXT: %nested_li_1 = "riscv.li"() {"immediate" = 1 : si32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %nested_li_1 = "riscv.li"() {"immediate" = 1 : i32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: }) {"directive" = ".text"} : () -> ()
// CHECK-GENERIC-NEXT: %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {"instruction_name" = "hello"} : (!riscv.reg<>, !riscv.reg<>) -> (!riscv.reg<>, !riscv.reg<>)
// CHECK-GENERIC-NEXT: %f0 = "riscv.get_float_register"() : () -> !riscv.freg<>
Expand Down Expand Up @@ -464,10 +464,10 @@
// CHECK-GENERIC-NEXT: %fcvt_s_w = "riscv.fcvt.s.w"(%0) : (!riscv.reg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: %fcvt_s_wu = "riscv.fcvt.s.wu"(%0) : (!riscv.reg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: %fmv_w_x = "riscv.fmv.w.x"(%0) : (!riscv.reg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: %flw = "riscv.flw"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: "riscv.fsw"(%0, %f0) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.freg<>) -> ()
// CHECK-GENERIC-NEXT: %fld = "riscv.fld"(%0) {"immediate" = 1 : si12} : (!riscv.reg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: "riscv.fsd"(%0, %f0) {"immediate" = 1 : si12} : (!riscv.reg<>, !riscv.freg<>) -> ()
// CHECK-GENERIC-NEXT: %flw = "riscv.flw"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: "riscv.fsw"(%0, %f0) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.freg<>) -> ()
// CHECK-GENERIC-NEXT: %fld = "riscv.fld"(%0) {"immediate" = 1 : i12} : (!riscv.reg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: "riscv.fsd"(%0, %f0) {"immediate" = 1 : i12} : (!riscv.reg<>, !riscv.freg<>) -> ()
// CHECK-GENERIC-NEXT: %fmv_d = "riscv.fmv.d"(%f0) : (!riscv.freg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: %vfadd_s = "riscv.vfadd.s"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
// CHECK-GENERIC-NEXT: %vfmul_s = "riscv.vfmul.s"(%f0, %f1) : (!riscv.freg<>, !riscv.freg<>) -> !riscv.freg<>
Expand Down
2 changes: 1 addition & 1 deletion tests/filecheck/dialects/riscv_snitch/ops.mlir
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Expand Up @@ -61,7 +61,7 @@ riscv_func.func @main() {
// CHECK-GENERIC-NEXT: %0 = "riscv.get_register"() : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %1 = "riscv.get_register"() : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %scfgw = "riscv_snitch.scfgw"(%0, %1) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<zero>
// CHECK-GENERIC-NEXT: %scfgwi_zero = "riscv_snitch.scfgwi"(%0) {"immediate" = 42 : si12} : (!riscv.reg<>) -> !riscv.reg<zero>
// CHECK-GENERIC-NEXT: %scfgwi_zero = "riscv_snitch.scfgwi"(%0) {"immediate" = 42 : i12} : (!riscv.reg<>) -> !riscv.reg<zero>
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_outer"(%{{.*}}) ({
// CHECK-GENERIC-NEXT: %{{.*}} = "riscv.add"(%{{.*}}, %{{.*}}) : (!riscv.reg<>, !riscv.reg<>) -> !riscv.reg<>
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_yield"() : () -> ()
Expand Down
2 changes: 1 addition & 1 deletion tests/filecheck/dialects/snitch_stream/ops.mlir
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Expand Up @@ -44,7 +44,7 @@
// CHECK-GENERIC-NEXT: %Z_str = "snitch_stream.strided_write"(%Z, %pattern) {"dm" = #builtin.int<2>, "rank" = #builtin.int<2>} : (!riscv.reg<>, !snitch_stream.stride_pattern_type<2>) -> !stream.writable<!riscv.freg<>>
// CHECK-GENERIC-NEXT: "snitch_stream.streaming_region"(%X, %Y, %Z, %pattern) <{"operandSegmentSizes" = array<i32: 2, 1, 1>}> ({
// CHECK-GENERIC-NEXT: ^0(%a_stream : !stream.readable<!riscv.freg<ft0>>, %b_stream : !stream.readable<!riscv.freg<ft1>>, %c_stream : !stream.writable<!riscv.freg<ft2>>):
// CHECK-GENERIC-NEXT: %c5 = "riscv.li"() {"immediate" = 5 : si32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: %c5 = "riscv.li"() {"immediate" = 5 : i32} : () -> !riscv.reg<>
// CHECK-GENERIC-NEXT: "riscv_snitch.frep_outer"(%c5) ({
// CHECK-GENERIC-NEXT: %a = "riscv_snitch.read"(%a_stream) : (!stream.readable<!riscv.freg<ft0>>) -> !riscv.freg<ft0>
// CHECK-GENERIC-NEXT: %b = "riscv_snitch.read"(%b_stream) : (!stream.readable<!riscv.freg<ft1>>) -> !riscv.freg<ft1>
Expand Down
6 changes: 3 additions & 3 deletions tests/test_attribute_definition.py
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Original file line number Diff line number Diff line change
Expand Up @@ -226,13 +226,13 @@ def test_unsigned_integer_attr():
def test_signless_integer_attr():
"""Test the verification of a signless integer attribute."""
with pytest.raises(VerifyException):
IntegerAttr((1 << 32) + 1, IntegerType(32, Signedness.SIGNLESS))
IntegerAttr((1 << 32), IntegerType(32, Signedness.SIGNLESS))

with pytest.raises(VerifyException):
IntegerAttr(-(1 << 32) - 1, IntegerType(32, Signedness.SIGNLESS))

IntegerAttr(1 << 32, IntegerType(32, Signedness.SIGNLESS))
IntegerAttr(-(1 << 32), IntegerType(32, Signedness.SIGNLESS))
IntegerAttr(1 << 32 - 1, IntegerType(32, Signedness.SIGNLESS))
IntegerAttr(-(1 << 31), IntegerType(32, Signedness.SIGNLESS))


################################################################################
Expand Down
10 changes: 5 additions & 5 deletions tests/test_op_builder.py
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Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@
def test_insertion_point_constructors():
target = Block(
[
(op1 := Constant.from_int_and_width(1, 1)),
(op2 := Constant.from_int_and_width(2, 1)),
(op1 := Constant.from_int_and_width(0, 1)),
(op2 := Constant.from_int_and_width(1, 1)),
]
)

Expand All @@ -37,16 +37,16 @@ def test_insertion_point_constructors():
def test_builder():
target = Block(
[
Constant.from_int_and_width(0, 1),
Constant.from_int_and_width(1, 1),
Constant.from_int_and_width(2, 1),
]
)

block = Block()
b = Builder.at_end(block)

x = Constant.from_int_and_width(1, 1)
y = Constant.from_int_and_width(2, 1)
x = Constant.from_int_and_width(0, 1)
y = Constant.from_int_and_width(1, 1)

b.insert(x)
b.insert(y)
Expand Down
86 changes: 49 additions & 37 deletions xdsl/dialects/builtin.py
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
overload,
)

from typing_extensions import Self, assert_never
from typing_extensions import Self

from xdsl.ir import (
Attribute,
Expand Down Expand Up @@ -304,6 +304,27 @@ class Signedness(Enum):
SIGNED = 1
UNSIGNED = 2

def value_range(self, bitwidth: int) -> tuple[int, int]:
"""
For a given bitwidth, returns (min, max+1), where min and max are the smallest and
largest representable values.

Signless integers are bit patterns, so the representable range is the union of the
signed and unsigned representable ranges.
"""
match self:
case Signedness.SIGNLESS:
min_value = -(1 << (bitwidth - 1))
max_value = 1 << bitwidth
case Signedness.SIGNED:
min_value = -(1 << (bitwidth - 1))
max_value = 1 << (bitwidth - 1)
case Signedness.UNSIGNED:
min_value = 0
max_value = 1 << bitwidth

return min_value, max_value


@irdl_attr_definition
class SignednessAttr(Data[Signedness]):
Expand Down Expand Up @@ -350,6 +371,9 @@ def __init__(
signedness = SignednessAttr(signedness)
super().__init__([data, signedness])

def value_range(self) -> tuple[int, int]:
return self.signedness.data.value_range(self.width.data)


i64 = IntegerType(64)
i32 = IntegerType(32)
Expand Down Expand Up @@ -432,36 +456,17 @@ def from_int_and_width(value: int, width: int) -> IntegerAttr[IntegerType]:
def from_index_int_value(value: int) -> IntegerAttr[IndexType]:
return IntegerAttr(value, IndexType())

@staticmethod
def _get_value_range(int_type: IntegerType) -> tuple[int, int]:
signedness = int_type.signedness.data
width = int_type.width.data

if signedness == Signedness.SIGNLESS:
min_value = -(1 << width)
max_value = 1 << width
elif signedness == Signedness.SIGNED:
min_value = -(1 << (width - 1))
max_value = (1 << (width - 1)) - 1
elif signedness == Signedness.UNSIGNED:
min_value = 0
max_value = (1 << width) - 1
else:
assert_never(signedness)

return min_value, max_value

def verify(self) -> None:
if isinstance(int_type := self.type, IndexType):
return

min_value, max_value = self._get_value_range(int_type)
min_value, max_value = int_type.value_range()

if not (min_value <= self.value.data <= max_value):
if not (min_value <= self.value.data < max_value):
raise VerifyException(
f"Integer value {self.value.data} is out of range for "
f"type {self.type} which supports values in the "
f"range [{min_value}, {max_value}]"
f"range [{min_value}, {max_value})"
)


Expand Down Expand Up @@ -967,9 +972,11 @@ def create_dense_float(
@staticmethod
def from_list(
type: RankedVectorOrTensorOf[AnyFloat | IntegerType | IndexType],
data: Sequence[int]
| Sequence[IntegerAttr[IndexType]]
| Sequence[IntegerAttr[IntegerType]],
data: (
Sequence[int]
| Sequence[IntegerAttr[IndexType]]
| Sequence[IntegerAttr[IntegerType]]
),
) -> DenseIntOrFPElementsAttr:
...

Expand Down Expand Up @@ -1013,11 +1020,13 @@ def vector_from_list(

@staticmethod
def tensor_from_list(
data: Sequence[int]
| Sequence[float]
| Sequence[IntegerAttr[IndexType]]
| Sequence[IntegerAttr[IntegerType]]
| Sequence[AnyFloatAttr],
data: (
Sequence[int]
| Sequence[float]
| Sequence[IntegerAttr[IndexType]]
| Sequence[IntegerAttr[IntegerType]]
| Sequence[AnyFloatAttr]
),
data_type: IntegerType | IndexType | AnyFloat,
shape: Sequence[int],
) -> DenseIntOrFPElementsAttr:
Expand Down Expand Up @@ -1103,10 +1112,12 @@ def from_list(
@staticmethod
def from_list(
data_type: Attribute,
data: Sequence[int]
| Sequence[int | float]
| Sequence[IntAttr]
| Sequence[FloatData],
data: (
Sequence[int]
| Sequence[int | float]
| Sequence[IntAttr]
| Sequence[FloatData]
),
) -> DenseArrayBase:
if isinstance(data_type, IndexType | IntegerType):
_data = cast(Sequence[int] | Sequence[IntAttr], data)
Expand Down Expand Up @@ -1180,8 +1191,9 @@ class StridedLayoutAttr(ParametrizedAttribute):

def __init__(
self,
strides: ArrayAttr[IntAttr | NoneAttr]
| Sequence[int | None | IntAttr | NoneAttr],
strides: (
ArrayAttr[IntAttr | NoneAttr] | Sequence[int | None | IntAttr | NoneAttr]
),
offset: int | None | IntAttr | NoneAttr = 0,
) -> None:
if not isinstance(strides, ArrayAttr):
Expand Down
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