dialects: (riscv) fix signedness in riscv

[superlopuh]

We currently have some inconsistencies/inaccuracies in the bitwidths in the riscv dialect, this PR attempts to make things more structured. We have 6 kinds of immediate values:

1. ui5 for shifting ops, we can only shift by a positive value
2. si12 and si20 for jump ops, where we want to be explicit about jumping by a negative number of ops
3. i12, i20, and i32 when the immediate values represent bits as they will be loaded into a register

This will make reasoning about constant values much easier, and will help fix some bugs in canonicalization

[codecov]

Codecov Report

Attention: 3 lines in your changes are missing coverage. Please review.

Comparison is base (6a53c04) 90.10% compared to head (5942103) 90.09%.
Report is 4 commits behind head on main.

Files	Patch %	Lines
xdsl/dialects/riscv.py	95.34%	1 Missing and 1 partial ⚠️
xdsl/dialects/builtin.py	94.11%	0 Missing and 1 partial ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #2100      +/-   ##
==========================================
- Coverage   90.10%   90.09%   -0.01%     
==========================================
  Files         295      295              
  Lines       36716    36750      +34     
  Branches     5454     5458       +4     
==========================================
+ Hits        33082    33109      +27     
- Misses       2854     2858       +4     
- Partials      780      783       +3     

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