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dialects: (x86) PR10 - RRI Operations #2524

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merged 4 commits into from
May 2, 2024
Merged

dialects: (x86) PR10 - RRI Operations #2524

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0562dcf
added support for RRI operations
KGrykiel May 2, 2024
fbc0140
Update tests/filecheck/dialects/x86/x86_assembly_emission.mlir
KGrykiel May 2, 2024
90ea342
Update tests/filecheck/dialects/x86/x86_ops.mlir
KGrykiel May 2, 2024
03aebb8
Update xdsl/dialects/x86/ops.py
KGrykiel May 2, 2024
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3 changes: 3 additions & 0 deletions tests/filecheck/dialects/x86/x86_assembly_emission.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -84,3 +84,6 @@ x86.mi.xor %0, 2, 8 : (!x86.reg<rax>) -> ()
// CHECK: xor [rax+8], 2
x86.mi.mov %0, 2, 8 : (!x86.reg<rax>) -> ()
// CHECK: mov [rax+8], 2

%rri_imul = x86.rri.imul %1, 2 : (!x86.reg<rdx>) -> !x86.reg<rax>
// CHECK: imul rax, rdx, 2
3 changes: 3 additions & 0 deletions tests/filecheck/dialects/x86/x86_ops.mlir
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Expand Up @@ -85,3 +85,6 @@ x86.mi.xor %0, 2, 8 : (!x86.reg<>) -> ()
// CHECK-NEXT: x86.mi.xor %{{.*}}, 2, 8 : (!x86.reg<>) -> ()
x86.mi.mov %0, 2, 8 : (!x86.reg<>) -> ()
// CHECK-NEXT: x86.mi.mov %{{.*}}, 2, 8 : (!x86.reg<>) -> ()

%rri_imul = x86.rri.imul %1, 2 : (!x86.reg<>) -> !x86.reg<>
// CHECK-NEXT: %{{.*}} = x86.rri.imul %{{.*}}, 2 : (!x86.reg<>) -> !x86.reg<>
2 changes: 2 additions & 0 deletions xdsl/dialects/x86/__init__.py
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Expand Up @@ -37,6 +37,7 @@
RR_OrOp,
RR_SubOp,
RR_XorOp,
RRI_ImulOP,
)
from .register import GeneralRegisterType

Expand Down Expand Up @@ -78,6 +79,7 @@
MI_OrOp,
MI_XorOp,
MI_MovOp,
RRI_ImulOP,
GetRegisterOp,
],
[
Expand Down
61 changes: 61 additions & 0 deletions xdsl/dialects/x86/ops.py
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Expand Up @@ -948,6 +948,67 @@ class MI_MovOp(M_MI_Operation[GeneralRegisterType]):
name = "x86.mi.mov"


class R_RRI_Operation(Generic[R1InvT, R2InvT], IRDLOperation, X86Instruction, ABC):
"""
A base class for x86 operations that have one destination register, one source register and an immediate value.
"""

r2 = operand_def(R2InvT)
immediate: AnyIntegerAttr = attr_def(AnyIntegerAttr)
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Does x86 specify the bitcount of the immediate values?

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image
According to the x86 manual immediates can only have 8, 16 or 32 bits (with 32 being the default I believe) with 64 bit immediates only appearing for rare instructions afaik.

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image
The configuration im targetting also implies a 32 bit immediate

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Ok, feels like we might want to encode that at some point, but not urgently

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good to merge then?


r1 = result_def(R1InvT)

def __init__(
self,
r2: Operation | SSAValue,
immediate: int | AnyIntegerAttr,
*,
comment: str | StringAttr | None = None,
r1: R1InvT,
):
if isinstance(immediate, int):
immediate = IntegerAttr(
immediate, 32
) # the default immediate size is 32 bits
if isinstance(comment, str):
comment = StringAttr(comment)

super().__init__(
operands=[r2],
attributes={
"immediate": immediate,
"comment": comment,
},
result_types=[r1],
)

def assembly_line_args(self) -> tuple[AssemblyInstructionArg | None, ...]:
return self.r1, self.r2, self.immediate

@classmethod
def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
attributes = dict[str, Attribute]()
temp = _parse_immediate_value(parser, IntegerType(32, Signedness.SIGNED))
attributes["immediate"] = temp
return attributes

def custom_print_attributes(self, printer: Printer) -> Set[str]:
printer.print(", ")
_print_immediate_value(printer, self.immediate)
return {"immediate"}


@irdl_op_definition
class RRI_ImulOP(R_RRI_Operation[GeneralRegisterType, GeneralRegisterType]):
"""
Multiplies the immediate value with the source register and stores the result in the destination register.
x[r1] = x[r2] * immediate
https://www.felixcloutier.com/x86/imul
"""

name = "x86.rri.imul"


# region Assembly printing
def _append_comment(line: str, comment: StringAttr | None) -> str:
if comment is None:
Expand Down
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