backend: (riscv) riscv-prologue-epilogue-insertion

tests/filecheck/backend/riscv/prologue_epilogue_insertion.mlir

@@ -50,3 +50,43 @@ riscv_func.func @main() {
 // CHECK-SMALL-FLEN: func @main
 // CHECK-SMALL-FLEN: addi %{{.*}}, -8
 // CHECK-SMALL-FLEN-SAME: (!riscv.reg<sp>) -> !riscv.reg<sp>
+
+// CHECK: func @simple
+riscv_func.func @simple(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) -> !riscv.reg<a0> {
+  // CHECK-NOT: %{{.*}} = riscv.get_register : () -> !riscv.reg<sp>
+  // CHECK-NOT: %{{.*}} = riscv.addi %{{.*}}, 0 : (!riscv.reg<sp>) -> !riscv.reg<sp>
+
+  // CHECK-NEXT: %{{.*}} = riscv.mv %{{.*}}
+  // CHECK-SAME: (!riscv.reg<a0>) -> !riscv.reg<t0>
+  %2 = riscv.mv %0 : (!riscv.reg<a0>) -> !riscv.reg<t0>
+  %3 = riscv.mv %1 : (!riscv.reg<a1>) -> !riscv.reg<t2>
+  %4 = riscv.li 10 : () -> !riscv.reg<t1>
+  %5 = riscv.add %2, %3 : (!riscv.reg<t0>, !riscv.reg<t2>) -> !riscv.reg<t0>
+  %6 = riscv.add %5, %4 : (!riscv.reg<t0>, !riscv.reg<t1>) -> !riscv.reg<t0>
+  %7 = riscv.mv %6 : (!riscv.reg<t0>) -> !riscv.reg<a0>
+
+  // CHECK-NOT: %{{.*}} = riscv.addi %{{.*}}, 0 : (!riscv.reg<sp>) -> !riscv.reg<sp>
+
+  // CHECK: riscv_func.return %{{.*}}
+  // CHECK-SAME: !riscv.reg<a0>
+  riscv_func.return %7 : !riscv.reg<a0>
+}
+
+// CHECK: func @simplefp
+riscv_func.func @simplefp(%0 : !riscv.freg<fa0>, %1 : !riscv.freg<fa1>) -> !riscv.freg<fa0> {
+  // CHECK-NOT: %{{.*}} = riscv.get_register : () -> !riscv.reg<sp>
+  // CHECK-NOT: %{{.*}} = riscv.addi %{{.*}}, 0 : (!riscv.reg<sp>) -> !riscv.reg<sp>
+
+  // CHECK-NEXT: %{{.*}} = riscv.fmv.s %{{.*}}
+  // CHECK-SAME: %{{.*}} = (!riscv.freg<fa0>) -> !riscv.freg<ft0>
+  %2 = riscv.fmv.s %0 : (!riscv.freg<fa0>) -> !riscv.freg<ft0>
+  %3 = riscv.fmv.s %1 : (!riscv.freg<fa1>) -> !riscv.freg<ft1>
+  %4 = riscv.fadd.s %2, %3 : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft0>
+  %5 = riscv.fmv.s %4 : (!riscv.freg<ft0>) -> !riscv.freg<fa0>
+
+  // CHECK-NOT: %{{.*}} = riscv.addi %{{.*}}, 0 : (!riscv.reg<sp>) -> !riscv.reg<sp>
+
+  // CHECK: riscv_func.return %{{.*}}
+  // CHECK-SAME: !riscv.freg<fa0>
+  riscv_func.return %5 : !riscv.freg<fa0>
+}

tests/interactive/test_get_all_available_passes.py

@@ -1,4 +1,3 @@
-from xdsl.backend.riscv import prologue_epilogue_insertion
 from xdsl.backend.riscv.lowering import (
     convert_arith_to_riscv,
     convert_func_to_riscv_func,
@@ -38,11 +37,6 @@ def test_get_all_available_passes():
                 module_pass=reconcile_unrealized_casts.ReconcileUnrealizedCastsPass,
                 pass_spec=None,
             ),
-            AvailablePass(
-                display_name="riscv-prologue-epilogue-insertion",
-                module_pass=prologue_epilogue_insertion.PrologueEpilogueInsertion,
-                pass_spec=None,
-            ),
         )
     )
 

xdsl/backend/riscv/prologue_epilogue_insertion.py

@@ -42,6 +42,9 @@ def _process_function(self, func: riscv_func.FuncOp) -> None:
             if res.type in Registers.S or res.type in Registers.FS
         )
 
+        if not used_callee_preserved_registers:
+            return
+
         def get_register_size(r: RISCVRegisterType):
             if isinstance(r, IntRegisterType):
                 return self.xlen