pip prod(deps): bump pyright from 1.1.393 to 1.1.394

pyproject.toml

@@ -29,7 +29,7 @@ dev = [
     "nbconvert>=7.7.2,<8.0.0",
     "textual-dev==1.7.0",
     "pytest-asyncio==0.25.3",
-    "pyright==1.1.393",
+    "pyright==1.1.394",
     "sympy==1.13.3",
 ]
 docs = [

xdsl/backend/riscv/prologue_epilogue_insertion.py

@@ -6,6 +6,7 @@
 from xdsl.context import MLContext
 from xdsl.dialects import builtin, riscv, riscv_func
 from xdsl.dialects.riscv import (
+    FloatRegisterType,
     IntRegisterType,
     Registers,
     RISCVRegisterType,
@@ -39,6 +40,7 @@ def _process_function(self, func: riscv_func.FuncOp) -> None:
             for op in func.walk()
             if not isinstance(op, riscv.GetRegisterOp | riscv.GetFloatRegisterOp)
             for res in op.results
+            if isinstance(res.type, IntRegisterType | FloatRegisterType)
             if res.type in Registers.S or res.type in Registers.FS
         )
 

xdsl/backend/riscv/riscv_register_queue.py

@@ -131,7 +131,7 @@ def exclude_register(self, reg: IntRegisterType | FloatRegisterType) -> None:
         """
         Removes register from available set, if present.
         """
-        if reg in self.available_int_registers:
+        if isinstance(reg, IntRegisterType) and reg in self.available_int_registers:
             self.available_int_registers.remove(reg)
-        if reg in self.available_float_registers:
+        if isinstance(reg, FloatRegisterType) and reg in self.available_float_registers:
             self.available_float_registers.remove(reg)

xdsl/transforms/convert_stencil_to_csl_stencil.py

@@ -302,15 +302,17 @@ def split_ops(
                         rem.remove(use.operation)
 
     # find constants in `a` needed outside of `a`
-    cnst_exports = [cnst for cnst in a_exports if isinstance(cnst, arith.ConstantOp)]
+    cnst_exports = tuple(
+        cnst for cnst in a_exports if isinstance(cnst, arith.ConstantOp)
+    )
 
     # `a` exports one value plus any number of constants - duplicate exported constants and return op split
     if len(a_exports) == 1 + len(cnst_exports):
         recv_chunk_ops, done_exch_ops = list[Operation](), list[Operation]()
         for op in ops:
             if op in a:
                 recv_chunk_ops.append(op)
-                if op in cnst_exports:
+                if op in cnst_exports and isinstance(op, arith.ConstantOp):
                     # create a copy of the constant in the second region
                     done_exch_ops.append(cln := op.clone())
                     # rewire ops of the second region to use the copied constant

xdsl/transforms/lower_csl_stencil.py

@@ -503,10 +503,9 @@ def match_and_rewrite(self, op: csl_stencil.ApplyOp, rewriter: PatternRewriter,
             rewriter.erase_op(e, safe_erase=False)
 
         # housekeeping: this strategy requires zeroing out the accumulator iff the apply is inside a loop
-        assert (elem_t := accumulator.type.get_element_type()) in [
-            Float16Type(),
-            Float32Type(),
-        ]
+        assert isinstance(
+            (elem_t := accumulator.type.get_element_type()), Float16Type | Float32Type
+        )
         zero = arith.ConstantOp(FloatAttr(0.0, elem_t))
         mov_op = csl.FmovsOp if elem_t == Float32Type() else csl.FmovhOp
         rewriter.insert_op(