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backend: (riscv) rename jx registers to j_x #3934

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Feb 19, 2025
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backend: (riscv) rename jx registers to j_x #3934

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18 changes: 9 additions & 9 deletions tests/backend/riscv/test_register_allocation.py
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ def test_default_reserved_registers():
unallocated = riscv.Registers.UNALLOCATED_INT

def j(index: int):
return riscv.IntRegisterType(f"j{index}")
return riscv.IntRegisterType(f"j_{index}")

assert register_queue.pop(riscv.IntRegisterType) == j(0)

Expand Down Expand Up @@ -62,7 +62,7 @@ def j(index: int):
with pytest.raises(
DiagnosticException,
match=re.escape(
"Cannot allocate registers to the same register ['!riscv.reg<j2>', '!riscv.reg<j3>']"
"Cannot allocate registers to the same register ['!riscv.reg<j_2>', '!riscv.reg<j_3>']"
),
):
register_allocator.allocate_same((d0, d1))
Expand All @@ -74,7 +74,7 @@ def j(index: int):
with pytest.raises(
DiagnosticException,
match=re.escape(
"Cannot allocate registers to the same register ['!riscv.reg', '!riscv.reg<j2>', '!riscv.reg<j3>']"
"Cannot allocate registers to the same register ['!riscv.reg', '!riscv.reg<j_2>', '!riscv.reg<j_3>']"
),
):
register_allocator.allocate_same((e0, e1, e2))
Expand Down Expand Up @@ -116,18 +116,18 @@ def get_register_constraints(self) -> RegisterConstraints:
# All new registers. The result register is reused by the allocator for the operand.
op0 = MyInstructionOp.get("", "", "", "")
register_allocator.process_riscv_op(op0)
assert op0.rs0.type == riscv.IntRegisterType("j1")
assert op0.rs1.type == riscv.IntRegisterType("j0")
assert op0.rd0.type == riscv.IntRegisterType("j1")
assert op0.rd1.type == riscv.IntRegisterType("j0")
assert op0.rs0.type == riscv.IntRegisterType("j_1")
assert op0.rs1.type == riscv.IntRegisterType("j_0")
assert op0.rd0.type == riscv.IntRegisterType("j_1")
assert op0.rd1.type == riscv.IntRegisterType("j_0")

# One register reserved for inout parameter, the allocator should allocate the output
# to the same register.
op1 = MyInstructionOp.get("", "", "", "a0")
register_allocator.process_riscv_op(op1)
assert op1.rs0.type == riscv.IntRegisterType("j2")
assert op1.rs0.type == riscv.IntRegisterType("j_2")
assert op1.rs1.type == riscv.IntRegisterType("a0")
assert op1.rd0.type == riscv.IntRegisterType("j2")
assert op1.rd0.type == riscv.IntRegisterType("j_2")
assert op1.rd1.type == riscv.IntRegisterType("a0")


Expand Down
28 changes: 15 additions & 13 deletions tests/backend/riscv/test_register_queue.py
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Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,13 @@ def test_default_reserved_registers():
def test_push_j_register():
register_queue = RiscvRegisterQueue()

register_queue.push(riscv.IntRegisterType("j0"))
assert riscv.IntRegisterType("j0") == register_queue.available_int_registers[-1]
register_queue.push(riscv.IntRegisterType("j_0"))
assert riscv.IntRegisterType("j_0") == register_queue.available_int_registers[-1]

register_queue.push(riscv.FloatRegisterType("j0"))
assert riscv.FloatRegisterType("j0") == register_queue.available_float_registers[-1]
register_queue.push(riscv.FloatRegisterType("j_0"))
assert (
riscv.FloatRegisterType("j_0") == register_queue.available_float_registers[-1]
)


def test_push_register():
Expand All @@ -45,18 +47,18 @@ def test_push_register():
def test_reserve_register():
register_queue = RiscvRegisterQueue()

register_queue.reserve_register(riscv.IntRegisterType("j0"))
assert register_queue.reserved_int_registers[riscv.IntRegisterType("j0")] == 1
register_queue.reserve_register(riscv.IntRegisterType("j_0"))
assert register_queue.reserved_int_registers[riscv.IntRegisterType("j_0")] == 1

register_queue.reserve_register(riscv.IntRegisterType("j0"))
assert register_queue.reserved_int_registers[riscv.IntRegisterType("j0")] == 2
register_queue.reserve_register(riscv.IntRegisterType("j_0"))
assert register_queue.reserved_int_registers[riscv.IntRegisterType("j_0")] == 2

register_queue.unreserve_register(riscv.IntRegisterType("j0"))
assert register_queue.reserved_int_registers[riscv.IntRegisterType("j0")] == 1
register_queue.unreserve_register(riscv.IntRegisterType("j_0"))
assert register_queue.reserved_int_registers[riscv.IntRegisterType("j_0")] == 1

register_queue.unreserve_register(riscv.IntRegisterType("j0"))
assert riscv.IntRegisterType("j0") not in register_queue.reserved_int_registers
assert riscv.IntRegisterType("j0") not in register_queue.available_int_registers
register_queue.unreserve_register(riscv.IntRegisterType("j_0"))
assert riscv.IntRegisterType("j_0") not in register_queue.reserved_int_registers
assert riscv.IntRegisterType("j_0") not in register_queue.available_int_registers

# Check assertion error when reserving an available register
reg = register_queue.pop(riscv.IntRegisterType)
Expand Down
2 changes: 1 addition & 1 deletion tests/dialects/test_riscv.py
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ def test_add_op():
assert a2.type.index == IntAttr(12)

# Registers that aren't predefined should not have an index.
assert isinstance(riscv.IntRegisterType("j1").index, NoneAttr)
assert isinstance(riscv.IntRegisterType("j_1").index, NoneAttr)


def test_csr_op():
Expand Down
8 changes: 4 additions & 4 deletions tests/filecheck/backend/riscv/canonicalize.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ builtin.module {

%i3 = riscv.li 100 : !riscv.reg
%i4 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg
%i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j0>
"test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j0>) -> ()
%i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j_0>
"test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j_0>) -> ()

%f0, %f1, %f2 = "test.op"() : () -> (!riscv.freg<fa0>, !riscv.freg<fa1>, !riscv.freg)
%fo0 = riscv.fmv.s %f0 : (!riscv.freg<fa0>) -> !riscv.freg<fa0>
Expand Down Expand Up @@ -136,8 +136,8 @@ builtin.module {

// CHECK-NEXT: %i3 = riscv.li 100 : !riscv.reg
// CHECK-NEXT: %i4 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg
// CHECK-NEXT: %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j0>
// CHECK-NEXT: "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j0>) -> ()
// CHECK-NEXT: %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j_0>
// CHECK-NEXT: "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j_0>) -> ()

// CHECK-NEXT: %{{.*}}, %{{.*}}, %{{.*}} = "test.op"() : () -> (!riscv.freg<fa0>, !riscv.freg<fa1>, !riscv.freg)
// CHECK-NEXT: %{{.*}} = riscv.fmv.s %{{.*}} : (!riscv.freg<fa1>) -> !riscv.freg<fa2>
Expand Down
16 changes: 8 additions & 8 deletions tests/filecheck/backend/riscv/register-allocation/frep.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -39,17 +39,17 @@ riscv_func.func @main() {

// CHECK-LIVENESS-BLOCK-NAIVE-J: builtin.module {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_func.func @main() {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.li 6 : !riscv.reg<j1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.li 6 : !riscv.reg<j_1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.li 5 : !riscv.reg<s0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<j1>) -> !riscv.freg<fj0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<s0>) -> !riscv.freg<fj1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.fadd.s %{{\d+}}, %{{\d+}} : (!riscv.freg<fj0>, !riscv.freg<fj1>) -> !riscv.freg<fj0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.add %{{\d+}}, %{{\d+}} : (!riscv.reg<j1>, !riscv.reg<s0>) -> !riscv.reg<j0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<s0>) -> !riscv.freg<fj_1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.fadd.s %{{\d+}}, %{{\d+}} : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.add %{{\d+}}, %{{\d+}} : (!riscv.reg<j_1>, !riscv.reg<s0>) -> !riscv.reg<j_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_snitch.frep_outer %{{\d+}} {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: }
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv_snitch.frep_outer %{{\d+}} iter_args(%{{\d+}} = %{{\d+}}) -> (!riscv.reg<j0>) {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.mv %{{\d+}} : (!riscv.reg<j0>) -> !riscv.reg<j0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_snitch.frep_yield %{{\d+}} : !riscv.reg<j0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv_snitch.frep_outer %{{\d+}} iter_args(%{{\d+}} = %{{\d+}}) -> (!riscv.reg<j_0>) {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %{{\d+}} = riscv.mv %{{\d+}} : (!riscv.reg<j_0>) -> !riscv.reg<j_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_snitch.frep_yield %{{\d+}} : !riscv.reg<j_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: }
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_func.return
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: }
Expand Down
18 changes: 9 additions & 9 deletions tests/filecheck/backend/riscv/register-allocation/generic.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -52,17 +52,17 @@ riscv_func.func @main() {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_func.func @external() -> ()
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_func.func @main() {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %zero = riscv.li 0 : !riscv.reg<zero>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %0 = riscv.li 6 : !riscv.reg<j1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %0 = riscv.li 6 : !riscv.reg<j_1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %1 = riscv.li 5 : !riscv.reg<s0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %2 = riscv.fcvt.s.w %0 : (!riscv.reg<j1>) -> !riscv.freg<fj0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %3 = riscv.fcvt.s.w %1 : (!riscv.reg<s0>) -> !riscv.freg<fj1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %4 = riscv.fadd.s %2, %3 : (!riscv.freg<fj0>, !riscv.freg<fj1>) -> !riscv.freg<fj0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %5 = riscv.add %0, %1 : (!riscv.reg<j1>, !riscv.reg<s0>) -> !riscv.reg<j0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_scf.for %6 : !riscv.reg<j2> = %0 to %1 step %5 {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %2 = riscv.fcvt.s.w %0 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %3 = riscv.fcvt.s.w %1 : (!riscv.reg<s0>) -> !riscv.freg<fj_1>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %4 = riscv.fadd.s %2, %3 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %5 = riscv.add %0, %1 : (!riscv.reg<j_1>, !riscv.reg<s0>) -> !riscv.reg<j_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_scf.for %6 : !riscv.reg<j_2> = %0 to %1 step %5 {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: }
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %7 = riscv_scf.for %8 : !riscv.reg<j1> = %0 to %1 step %5 iter_args(%9 = %5) -> (!riscv.reg<j0>) {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %10 = riscv.mv %9 : (!riscv.reg<j0>) -> !riscv.reg<j0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_scf.yield %10 : !riscv.reg<j0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %7 = riscv_scf.for %8 : !riscv.reg<j_1> = %0 to %1 step %5 iter_args(%9 = %5) -> (!riscv.reg<j_0>) {
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %10 = riscv.mv %9 : (!riscv.reg<j_0>) -> !riscv.reg<j_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: riscv_scf.yield %10 : !riscv.reg<j_0>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: }
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %zero_1 = riscv.li 0 : !riscv.reg<zero>
// CHECK-LIVENESS-BLOCK-NAIVE-J-NEXT: %zero_2 = riscv.li 0 : !riscv.reg<a0>
Expand Down
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