Add support for QuickLogic EOS S3 SoC

CODEOWNERS

@@ -42,6 +42,7 @@
 /soc/arm/nuvoton/                         @ssekar15
 /soc/arm/nuvoton_npcx/                    @MulinChao
 /soc/arm/qemu_cortex_a53/                 @carlocaione
+/soc/arm/quicklogic_eos_s3/               @kowalewskijan @kgugala
 /soc/arm/silabs_exx32/efr32mg21/          @l-alfred
 /soc/arm/st_stm32/                        @erwango
 /soc/arm/st_stm32/stm32f4/                @idlethread
@@ -97,6 +98,7 @@
 /boards/arm/qemu_cortex_a53/              @carlocaione
 /boards/arm/qemu_cortex_r*/               @stephanosio
 /boards/arm/qemu_cortex_m*/               @ioannisg
+/boards/arm/quick_feather/                @kowalewskijan @kgugala
 /boards/arm/xmc45_relax_kit/              @parthitce
 /boards/arm/sam4e_xpro/                   @nandojve
 /boards/arm/sam4s_xplained/               @fallrisk
@@ -280,6 +282,7 @@
 /dts/arm/broadcom/                        @sbranden
 /dts/arm/infineon/                        @parthitce
 /dts/arm/qemu-virt/                       @carlocaione
+/dts/arm/quicklogic/                      @wtatarski @kowalewskijan @kgugala
 /dts/arm/st/                              @erwango
 /dts/arm/ti/cc13?2*                       @bwitherspoon
 /dts/arm/ti/cc26?2*                       @bwitherspoon

boards/arm/quick_feather/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_library_sources(board.c)
+zephyr_include_directories(.)

boards/arm/quick_feather/Kconfig

@@ -0,0 +1,10 @@
+# Quick Feather board
+
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INIT_PRIORITY
+	int
+	default KERNEL_INIT_PRIORITY_DEFAULT
+	help
+	  Board initialization priority.

boards/arm/quick_feather/Kconfig.board

@@ -0,0 +1,8 @@
+# Quick Feather board
+
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_QUICK_FEATHER
+	bool "QuickLogic Quick Feather target"
+	depends on SOC_EOS_S3

boards/arm/quick_feather/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# QuickLogic Quick Feather board
+
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_QUICK_FEATHER
+
+config BOARD
+	default "quick_feather"
+
+endif # BOARD_QUICK_FEATHER

boards/arm/quick_feather/board.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <soc.h>
+#include <board.h>
+
+static int eos_s3_board_init(const struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* IO MUX setup for UART */
+	eos_s3_io_mux(UART_TX_PAD, UART_TX_PAD_CFG);
+	eos_s3_io_mux(UART_RX_PAD, UART_RX_PAD_CFG);
+
+	IO_MUX->UART_rxd_SEL = UART_RX_SEL;
+
+	return 0;
+}
+
+SYS_INIT(eos_s3_board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);

boards/arm/quick_feather/board.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc_pinmap.h>
+
+#define UART_TX_PAD		44
+#define UART_TX_PAD_CFG		UART_TXD_PAD44
+#define UART_RX_PAD		45
+#define UART_RX_PAD_CFG		UART_RXD_PAD45
+
+#define UART_RX_SEL		UART_RXD_SEL_PAD45
+
+#endif /* __INC_BOARD_H */

boards/arm/quick_feather/quick_feather.dts

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <quicklogic/quicklogic_eos_s3.dtsi>
+
+/ {
+	model = "QuickLogic Quick Feather board";
+	compatible = "quicklogic,eos_s3";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-pipe = &uart0;
+	};
+
+};
+
+&cpu0 {
+	clock-frequency = <61440000>;
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+};

boards/arm/quick_feather/quick_feather.yaml

@@ -0,0 +1,12 @@
+identifier: quick_feather
+name: QuickLogic Quick Feather
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm/quick_feather/quick_feather_defconfig

@@ -0,0 +1,28 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=n
+CONFIG_SOC_EOS_S3=y
+CONFIG_BOARD_QUICK_FEATHER=y
+
+# system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=61440000
+CONFIG_CORTEX_M_SYSTICK=y
+
+# console
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_PRINTK=y
+CONFIG_UART_CONSOLE=y
+
+# misc
+CONFIG_BOOT_BANNER=y
+
+# EOS S3 Configuartion Manager copies software from external flash to MCU
+# memory using preconfigured DMA and execute it there.
+# Thus we do not use flash directly.
+
+CONFIG_XIP=n
+CONFIG_FLASH=n
+CONFIG_FLASH_SIZE=0
+CONFIG_FLASH_BASE_ADDRESS=0x0

dts/arm/quicklogic/quicklogic_eos_s3.dtsi

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SIZE_K(512)>;
+	};
+
+	uartclk: uart-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <5120000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		uart0: uart@40010000 {
+			compatible = "arm,pl011";
+			reg = <0x40010000 DT_SIZE_K(4)>;
+			clocks = <&uartclk>;
+			interrupts = <7 3>;
+			interrupt-names = "rx";
+			label = "UART_0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

dts/bindings/vendor-prefixes.txt

@@ -336,6 +336,7 @@ qemu	QEMU, a generic and open source machine emulator and virtualizer
 qi	Qi Hardware
 qiaodian	QiaoDian XianShi Corporation
 qnap	QNAP Systems, Inc.
+quicklogic	QuickLogic Corp.
 radxa	Radxa
 raidsonic	RaidSonic Technology GmbH
 ralink	Mediatek/Ralink Technology Corp.

modules/Kconfig

@@ -9,6 +9,7 @@ source "modules/Kconfig.canopennode"
 source "modules/Kconfig.civetweb"
 source "modules/Kconfig.cmsis"
 source "modules/Kconfig.cypress"
+source "modules/Kconfig.eos_s3"
 source "modules/Kconfig.imx"
 source "modules/Kconfig.infineon"
 source "modules/Kconfig.libmetal"

modules/Kconfig.eos_s3

@@ -0,0 +1,8 @@
+# QuickLogic HAL
+
+# Copyright (c) 2020 Antmicro Ltd <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config EOS_S3_HAL
+	bool
+	depends on SOC_EOS_S3

soc/arm/quicklogic_eos_s3/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  )

soc/arm/quicklogic_eos_s3/Kconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_EOS_S3
+	bool

soc/arm/quicklogic_eos_s3/Kconfig.defconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EOS_S3
+
+config SOC
+	default "quicklogic_eos_s3"
+
+config NUM_IRQS
+	default 52
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 61440000
+
+if SERIAL
+
+config UART_PL011
+	default y
+
+config UART_INTERRUPT_DRIVEN
+	default y
+
+config UART_PL011_PORT0
+	default y
+
+config UART_PL011_PORT1
+	default n
+
+endif # SERIAL
+
+endif # SOC_EOS_S3

soc/arm/quicklogic_eos_s3/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_EOS_S3
+	bool "QuickLogic EOS S3 SoC"
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_HAS_ARM_MPU
+	select EOS_S3_HAL

soc/arm/quicklogic_eos_s3/linker.ld

@@ -0,0 +1,7 @@
+/*
+# Copyright (c) 2020 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>