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Merged
merged 7 commits into from
Feb 2, 2024
Merged

STM32 nor flash controller gets address and size #68274

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0e335a2
dts: bindings: flash controller stm32 ospi nor flash reg property
FRASTM Jan 30, 2024
0756e0c
drivers: flash: stm32 ospi drivers gets address and size from DTS
FRASTM Jun 1, 2023
9b142c3
boards: arm: stm32 disco kit has ospi nor flash node
FRASTM Jan 25, 2024
ce0a567
dts: bindings: flash controller stm32 qspi nor flash reg property
FRASTM Jan 25, 2024
7e64369
drivers: flash: stm32 qspi drivers gets address and size from DTS
FRASTM Jan 30, 2024
8192b65
boards: arm: stm32 boards has qspi nor flash node
FRASTM Jan 25, 2024
a9f4a93
doc: releases:; migration guide updated
FRASTM Jan 30, 2024
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5 changes: 2 additions & 3 deletions boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts
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Expand Up @@ -171,11 +171,10 @@
pinctrl-names = "default";
status = "okay";

n25q128a1: qspi-nor-flash@0 {
n25q128a1: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(16*8)>;
status = "okay";

partitions {
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5 changes: 2 additions & 3 deletions boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi
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Expand Up @@ -131,11 +131,10 @@ stm32_lp_tick_source: &lptim1 {

status = "okay";

mx25lm51245: ospi-nor-flash@0 {
mx25lm51245: ospi-nor-flash@70000000 {
compatible = "st,stm32-ospi-nor";
reg = <0>;
reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
spi-bus-width = <OSPI_OPI_MODE>;
data-rate = <OSPI_DTR_TRANSFER>;
four-byte-opcodes;
Expand Down
6 changes: 2 additions & 4 deletions boards/arm/disco_l475_iot1/disco_l475_iot1.dts
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Expand Up @@ -321,12 +321,10 @@ zephyr_udc0: &usbotg_fs {

status = "okay";

mx25r6435f: qspi-nor-flash@0 {
mx25r6435f: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */
qspi-max-frequency = <50000000>;
/* 64 Megabits = 8 Megabytes */
size = <0x4000000>;
status = "okay";

partitions {
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5 changes: 2 additions & 3 deletions boards/arm/pandora_stm32l475/pandora_stm32l475.dts
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Expand Up @@ -79,11 +79,10 @@
pinctrl-names = "default";

status = "okay";
w25q128jv: qspi-nor-flash@0 {
w25q128jv: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
qspi-max-frequency = <80000000>;
size = <0x8000000>;
jedec-id = [ef 40 18];
spi-bus-width = <4>;
status = "okay";
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5 changes: 2 additions & 3 deletions boards/arm/stm32f412g_disco/stm32f412g_disco.dts
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Expand Up @@ -147,11 +147,10 @@
pinctrl-names = "default";
status = "okay";

n25q128a1: qspi-nor-flash@0 {
n25q128a1: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(16*8)>;
status = "okay";
};
};
5 changes: 2 additions & 3 deletions boards/arm/stm32f723e_disco/stm32f723e_disco.dts
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Expand Up @@ -124,11 +124,10 @@
flash-id = <1>;
status = "okay";

mx25r512: qspi-nor-flash@0 {
mx25r512: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <8000000>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
status = "okay";
spi-bus-width = <4>;
writeoc = "PP_1_4_4";
Expand Down
5 changes: 2 additions & 3 deletions boards/arm/stm32f746g_disco/stm32f746g_disco.dts
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Expand Up @@ -187,11 +187,10 @@ zephyr_udc0: &usbotg_fs {
pinctrl-names = "default";
status = "okay";

n25q128a1: qspi-nor-flash@0 {
n25q128a1: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(16*8)>;
status = "okay";

partitions {
Expand Down
5 changes: 2 additions & 3 deletions boards/arm/stm32f7508_dk/stm32f7508_dk.dts
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Expand Up @@ -183,11 +183,10 @@ zephyr_udc0: &usbotg_fs {
pinctrl-names = "default";
status = "okay";

n25q128a1: qspi-nor-flash@0 {
n25q128a1: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(16*8)>;
status = "okay";

partitions {
Expand Down
7 changes: 3 additions & 4 deletions boards/arm/stm32f769i_disco/stm32f769i_disco.dts
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Expand Up @@ -172,11 +172,10 @@ arduino_serial: &usart6 {};
pinctrl-names = "default";
status = "okay";

mx25l51245g: qspi-nor-flash@0 {
mx25l51245g: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(64*8)>;
status = "okay";

partitions {
Expand All @@ -186,7 +185,7 @@ arduino_serial: &usart6 {};

slot1_partition: partition@0 {
label = "image-1";
reg = <0x00000000 DT_SIZE_K(1664)>;
reg = <0x00000000 DT_SIZE_K(16)>;
};

storage_partition: partition@1a0000 {
Expand Down
10 changes: 4 additions & 6 deletions boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts
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Expand Up @@ -232,11 +232,10 @@ zephyr_udc0: &usbotg_hs {
pinctrl-names = "default";
status = "okay";

mt25ql512ab1: qspi-nor-flash-1@0 {
mt25ql512ab1: qspi-nor-flash-1@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
spi-bus-width = <4>;
status = "okay";

Expand All @@ -251,11 +250,10 @@ zephyr_udc0: &usbotg_hs {
};
};

mt25ql512ab2: qspi-nor-flash-2@0 {
mt25ql512ab2: qspi-nor-flash-2@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
status = "okay";
};
};
Expand Down
9 changes: 4 additions & 5 deletions boards/arm/stm32h750b_dk/stm32h750b_dk.dts
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Expand Up @@ -102,11 +102,10 @@
flash-id = <1>;
status = "okay";

mt25ql512ab1: qspi-nor-flash-1@0 {
mt25ql512ab1: qspi-nor-flash-1@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
spi-bus-width = <4>;
status = "okay";

Expand All @@ -121,9 +120,9 @@
};
};

mt25ql512ab2: qspi-nor-flash-2@1 {
mt25ql512ab2: qspi-nor-flash-2@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <1>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
status = "okay";
Expand Down
5 changes: 2 additions & 3 deletions boards/arm/stm32l496g_disco/stm32l496g_disco.dts
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Expand Up @@ -201,11 +201,10 @@ zephyr_udc0: &usbotg_fs {
flash-id = <1>;
status = "okay";

mx25r6435: qspi-nor-flash@0 {
mx25r6435: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */
qspi-max-frequency = <8000000>;
size = <DT_SIZE_M(64)>; /* 8 MBytes */
status = "okay";
spi-bus-width = <4>;
writeoc = "PP_1_4_4";
Expand Down
5 changes: 2 additions & 3 deletions boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi
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Expand Up @@ -135,11 +135,10 @@ stm32_lp_tick_source: &lptim1 {

status = "okay";

mx25lm51245: ospi-nor-flash@0 {
mx25lm51245: ospi-nor-flash@90000000 {
compatible = "st,stm32-ospi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
size = <DT_SIZE_M(512)>; /* 64 MBytes */
spi-bus-width = <OSPI_OPI_MODE>;
data-rate = <OSPI_DTR_TRANSFER>;
four-byte-opcodes;
Expand Down
12 changes: 12 additions & 0 deletions doc/releases/migration-guide-3.6.rst
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Expand Up @@ -166,6 +166,18 @@ Device Drivers and Device Tree
status = "okay";
};


* The :dtcompatible:`st,stm32-ospi-nor` and :dtcompatible:`st,stm32-qspi-nor` give the nor flash
base address and size (in Bytes) with the **reg** property as follows.
The <size> property is not used anymore.

.. code-block:: devicetree

mx25lm51245: ospi-nor-flash@70000000 {
compatible = "st,stm32-ospi-nor";
reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits*/
};

* The native Linux SocketCAN driver, which can now be used in both :ref:`native_posix<native_posix>`
and :ref:`native_sim<native_sim>` with or without an embedded C-library, has been renamed to
reflect this:
Expand Down
9 changes: 8 additions & 1 deletion drivers/flash/flash_stm32_ospi.c
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Expand Up @@ -36,6 +36,9 @@ LOG_MODULE_REGISTER(flash_stm32_ospi, CONFIG_FLASH_LOG_LEVEL);
(_CONCAT(HAL_OSPIM_, DT_STRING_TOKEN(STM32_OSPI_NODE, prop))), \
((default_value)))

/* Get the base address of the flash from the DTS node */
#define STM32_OSPI_BASE_ADDRESS DT_INST_REG_ADDR(0)

#define STM32_OSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios)

#define STM32_OSPI_DLYB_BYPASSED DT_PROP(STM32_OSPI_NODE, dlyb_bypass)
Expand Down Expand Up @@ -2235,6 +2238,10 @@ static int flash_stm32_ospi_init(const struct device *dev)
}
#endif /* CONFIG_FLASH_PAGE_LAYOUT */

LOG_INF("NOR octo-flash at 0x%lx (0x%x bytes)",
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@henrikbrixandersen henrikbrixandersen Feb 1, 2024

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Was this meant to use LOG_INF()?

(long)(STM32_OSPI_BASE_ADDRESS),
dev_cfg->flash_size);

return 0;
}

Expand Down Expand Up @@ -2300,7 +2307,7 @@ static const struct flash_stm32_ospi_config flash_stm32_ospi_cfg = {
.enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_mgr, bits)},
#endif
.irq_config = flash_stm32_ospi_irq_config_func,
.flash_size = DT_INST_PROP(0, size) / 8U,
.flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
.max_frequency = DT_INST_PROP(0, ospi_max_frequency),
.data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */
.data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */
Expand Down
9 changes: 8 additions & 1 deletion drivers/flash/flash_stm32_qspi.c
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Expand Up @@ -29,6 +29,9 @@
#define STM32_QSPI_USE_QUAD_IO 0
#endif

/* Get the base address of the flash from the DTS node */
#define STM32_QSPI_BASE_ADDRESS DT_INST_REG_ADDR(0)

#define STM32_QSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios)
#define STM32_QSPI_RESET_CMD DT_INST_NODE_HAS_PROP(0, reset_cmd)

Expand Down Expand Up @@ -1364,6 +1367,10 @@ static int flash_stm32_qspi_init(const struct device *dev)
}
#endif /* CONFIG_FLASH_PAGE_LAYOUT */

LOG_INF("NOR quad-flash at 0x%lx (0x%x bytes)",
(long)(STM32_QSPI_BASE_ADDRESS),
dev_cfg->flash_size);
Comment on lines +1370 to +1372
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@henrikbrixandersen henrikbrixandersen Feb 1, 2024

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Same here?


return 0;
}

Expand Down Expand Up @@ -1420,7 +1427,7 @@ static const struct flash_stm32_qspi_config flash_stm32_qspi_cfg = {
.bus = DT_CLOCKS_CELL(STM32_QSPI_NODE, bus)
},
.irq_config = flash_stm32_qspi_irq_config_func,
.flash_size = DT_INST_PROP(0, size) / 8U,
.flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
.max_frequency = DT_INST_PROP(0, qspi_max_frequency),
.pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_QSPI_NODE),
#if STM32_QSPI_RESET_GPIO
Expand Down
9 changes: 3 additions & 6 deletions dts/bindings/flash_controller/st,stm32-ospi-nor.yaml
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Expand Up @@ -6,13 +6,12 @@ description: |

Representation of a serial flash on a octospi bus:

mx25lm51245: ospi-nor-flash@0 {
mx25lm51245: ospi-nor-flash@70000000 {
compatible = "st,stm32-ospi-nor";
reg = <0>;
reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
ospi-max-frequency = <DT_FREQ_M(50)>;
size = <DT_SIZE_M(64*8)>; /* 512 Mbit */
status = "okay";
};

Expand All @@ -25,13 +24,11 @@ on-bus: ospi
properties:
reg:
required: true
description: Flash Memory base address and size in bytes
ospi-max-frequency:
type: int
required: true
description: Maximum clock frequency of device's OSPI interface in Hz
size:
required: true
description: Flash Memory size in bits
reset-gpios:
type: phandle-array
description: RESETn pin
Expand Down
9 changes: 3 additions & 6 deletions dts/bindings/flash_controller/st,stm32-qspi-nor.yaml
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Expand Up @@ -6,11 +6,10 @@ description: |

Representation of a serial flash on a quadspi bus:

mx25r6435f: qspi-nor-flash@0 {
mx25r6435f: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */
qspi-max-frequency = <80000000>;
size = <0x4000000>;
reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
reset-gpios-duration = <1>;
spi-bus-width = <4>;
Expand All @@ -26,13 +25,11 @@ on-bus: qspi
properties:
reg:
required: true
description: Flash Memory base address and size in bytes
qspi-max-frequency:
type: int
required: true
description: Maximum clock frequency of device's QSPI interface in Hz
size:
required: true
description: Flash Memory size in bits
reset-gpios:
type: phandle-array
description: RESETn pin
Expand Down
5 changes: 2 additions & 3 deletions samples/subsys/fs/littlefs/boards/nucleo_h743zi.overlay
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Expand Up @@ -23,11 +23,10 @@
flash-id = <2>;
status = "okay";

mx25l25645g: qspi-nor-flash@0 {
mx25l25645g: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0>;
reg = <0x90000000 DT_SIZE_M(32)>; /* 256 Mbits */
qspi-max-frequency = <50000000>;
size = <DT_SIZE_M(32*8)>;
reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
reset-gpios-duration = <1>;
spi-bus-width = <4>;
Expand Down