STM32F7 SoC family and STM32F746G Discovery board basic support

arch/arm/soc/st_stm32/stm32f7/CMakeLists.txt

@@ -0,0 +1,5 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

arch/arm/soc/st_stm32/stm32f7/Kconfig.defconfig.series

@@ -0,0 +1,31 @@
+# Kconfig.defconfig.series - ST Microelectronics STM32F7 MCU line
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F7X
+
+gsource "arch/arm/soc/st_stm32/stm32f7/Kconfig.defconfig.stm32f7*"
+
+config SOC_SERIES
+	default "stm32f7"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTH
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_SERIES_STM32F7X

arch/arm/soc/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xg

@@ -0,0 +1,28 @@
+# Kconfig - ST STM32F746XG MCU configuration options
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F746XG
+
+config SOC
+	string
+	default "stm32f746xx"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
+config NUM_IRQS
+	int
+	default 98
+
+endif # SOC_STM32F746XG

arch/arm/soc/st_stm32/stm32f7/Kconfig.series

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F7 MCU series
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F7X
+	bool "STM32F7x Series MCU"
+	select CPU_CORTEX_M7
+	select CPU_HAS_FPU
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_STM32CUBE
+	select CPU_HAS_SYSTICK
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
+	help
+	 Enable support for STM32F7 MCU series

arch/arm/soc/st_stm32/stm32f7/Kconfig.soc

@@ -0,0 +1,15 @@
+# Kconfig.soc - ST Microelectronics STM32F7 MCU line
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32F7x MCU Selection"
+depends on SOC_SERIES_STM32F7X
+
+config SOC_STM32F746XG
+	bool "STM32F746XG"
+
+endchoice

arch/arm/soc/st_stm32/stm32f7/dts.fixup

@@ -0,0 +1,53 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS	ST_STM32_USART_40011000_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_1_BAUD_RATE	ST_STM32_USART_40011000_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_1_IRQ_PRI	ST_STM32_USART_40011000_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_1_NAME		ST_STM32_USART_40011000_LABEL
+#define USART_1_IRQ				ST_STM32_USART_40011000_IRQ_0
+
+#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_2_NAME		ST_STM32_USART_40004400_LABEL
+#define USART_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS	ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_3_BAUD_RATE	ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_3_IRQ_PRI	ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_3_NAME		ST_STM32_USART_40004800_LABEL
+#define USART_3_IRQ				ST_STM32_USART_40004800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_4_BASE_ADDRESS	ST_STM32_USART_40004C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_4_BAUD_RATE	ST_STM32_USART_40004C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_4_IRQ_PRI	ST_STM32_USART_40004C00_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_4_NAME		ST_STM32_USART_40004C00_LABEL
+#define USART_4_IRQ				ST_STM32_USART_40004C00_IRQ_0
+
+#define CONFIG_UART_STM32_USART_5_BASE_ADDRESS	ST_STM32_USART_40005000_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_5_BAUD_RATE	ST_STM32_USART_40005000_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_5_IRQ_PRI	ST_STM32_USART_40005000_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_5_NAME		ST_STM32_USART_40005000_LABEL
+#define USART_5_IRQ				ST_STM32_USART_40005000_IRQ_0
+
+#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS	ST_STM32_USART_40011400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_6_BAUD_RATE	ST_STM32_USART_40011400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_6_IRQ_PRI	ST_STM32_USART_40011400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_6_NAME		ST_STM32_USART_40011400_LABEL
+#define USART_6_IRQ				ST_STM32_USART_40011400_IRQ_0
+
+#define CONFIG_UART_STM32_USART_7_BASE_ADDRESS	ST_STM32_USART_40007800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_7_BAUD_RATE	ST_STM32_USART_40007800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_7_IRQ_PRI	ST_STM32_USART_40007800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_7_NAME		ST_STM32_USART_40007800_LABEL
+#define USART_7_IRQ				ST_STM32_USART_40007800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_8_BASE_ADDRESS	ST_STM32_USART_40007C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_8_BAUD_RATE	ST_STM32_USART_40007C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_8_IRQ_PRI	ST_STM32_USART_40007C00_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_8_NAME		ST_STM32_USART_40007800_LABEL
+#define USART_8_IRQ				ST_STM32_USART_40007C00_IRQ_0
+
+/* End of SoC Level DTS fixup file */

arch/arm/soc/st_stm32/stm32f7/flash_registers.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F7X_FLASH_REGISTERS_H_
+#define _STM32F7X_FLASH_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   RM0385 Reference manual STM32F75xxx and STM32F74xxx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 3: Embedded Flash Memory
+ */
+
+union __flash_acr {
+	u32_t val;
+	struct {
+		u32_t latency :4 __packed;
+		u32_t rsvd__4_7 :4 __packed;
+		u32_t prften :1 __packed;
+		u32_t arten :1 __packed;
+		u32_t rsvd__10 :1 __packed;
+		u32_t artrst :1 __packed;
+		u32_t rsvd__12_31 :20 __packed;
+	} bit;
+};
+
+/* 3.7 FLASH registers */
+struct stm32f7x_flash {
+	volatile union __flash_acr acr;
+	volatile u32_t keyr;
+	volatile u32_t optkeyr;
+	volatile u32_t sr;
+	volatile u32_t cr;
+	volatile u32_t optcr;
+	volatile u32_t optcr1;
+};
+
+#endif	/* _STM32F7X_FLASHREGISTERS_H_ */

arch/arm/soc/st_stm32/stm32f7/gpio_registers.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F7X_GPIO_REGISTERS_H_
+#define _STM32F7X_GPIO_REGISTERS_H_
+
+/**
+ * @brief Driver for GPIO of STM32F7X family processor.
+ *
+ * Based on reference manual:
+ *   RM0385 Reference manual STM32F75xxx and STM32F74xxx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 6: General-purpose I/Os (GPIOs)
+ */
+
+/* 6.4 GPIO registers - each GPIO port controls 16 pins */
+struct stm32f7x_gpio {
+	u32_t moder;
+	u32_t otyper;
+	u32_t ospeedr;
+	u32_t pupdr;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t lckr;
+	u32_t afr[2];
+	u32_t brr;
+};
+
+union syscfg_exticr {
+	u32_t val;
+	struct {
+		u16_t rsvd__16_31;
+		u16_t exti;
+	} bit;
+};
+
+/* 7.2 SYSCFG registers */
+struct stm32f7x_syscfg {
+	u32_t memrmp;
+	u32_t pmc;
+	union syscfg_exticr exticr1;
+	union syscfg_exticr exticr2;
+	union syscfg_exticr exticr3;
+	union syscfg_exticr exticr4;
+	u32_t cmpcr;
+};
+
+#endif /* _STM32F7X_GPIO_REGISTERS_H_ */

arch/arm/soc/st_stm32/stm32f7/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/st_stm32/stm32f7/soc.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32F7 processor
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int st_stm32f7_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	_ClearFaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 16 MHz from HSI */
+	SystemCoreClock = 16000000;
+
+	return 0;
+}
+
+SYS_INIT(st_stm32f7_init, PRE_KERNEL_1, 0);

arch/arm/soc/st_stm32/stm32f7/soc.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the ST STM32F7 family processors.
+ *
+ * Based on reference manual:
+ * RM0385 Reference manual STM32F75xxx and STM32F74xxx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 2.2.2: Memory map and register boundary addresses
+ */
+
+#ifndef _STM32F7_SOC_H_
+#define _STM32F7_SOC_H_
+
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+#ifndef _ASMLANGUAGE
+
+#include <device.h>
+#include <misc/util.h>
+#include <stm32f7xx.h>
+
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f7xx_ll_utils.h>
+#include <stm32f7xx_ll_bus.h>
+#include <stm32f7xx_ll_rcc.h>
+#include <stm32f7xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
+#ifdef CONFIG_SERIAL_HAS_DRIVER
+#include <stm32f7xx_ll_usart.h>
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F7_SOC_H_ */