Feature/rt700 add multicore support cm33 cores

boards/nxp/mimxrt700_evk/Kconfig.defconfig

@@ -0,0 +1,26 @@
+# MIMXRT700-EVK board
+
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MIMXRT700_EVK
+
+if SECOND_CORE_MCUX && SOC_MIMXRT798S_CM33_CPU1
+
+config BUILD_OUTPUT_INFO_HEADER
+	default y
+
+# RT700 CPU1 LMA offset calculation:
+# CPU1 doesn't have access to flash partitions, so we use known values:
+# - CPU0 will store CPU1 image at flash offset 0x720000 (slot1_partition)
+# - Flash is memory-mapped at 0x28000000 (RT700 XSPI0 base)
+# - CPU1 executes from 0x600000 (CPU1 alias space)
+#
+# LMA = flash_base + partition_offset = 0x28000000 + 0x720000 = 0x28720000
+# Adjustment = LMA - VMA = 0x28720000 - 0x600000 = 0x28120000
+config BUILD_OUTPUT_ADJUST_LMA
+	default "0x28720000 - 0x00600000"
+
+endif
+
+endif

boards/nxp/mimxrt700_evk/board.c

@@ -147,6 +147,9 @@ void board_early_init_hook(void)
 	CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
 	CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
 
+	/* Enable clock for Hifi4 access RAM arbiter1 (for SRAM start from 0x2058000000) */
+	CLOCK_EnableClock(kCLOCK_Hifi4AccessRamArbiter1);
+
 #if CONFIG_FLASH_MCUX_XSPI_XIP
 	/* Call function xspi_setup_clock() to set user configured clock for XSPI. */
 	xspi_setup_clock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */
@@ -172,10 +175,17 @@ void board_early_init_hook(void)
 	CLOCK_AttachClk(kFRO2_DIV3_to_SENSE_BASE);
 	CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
 	CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
+
+	CLOCK_EnableClock(kCLOCK_SenseAccessRamArbiter0);
 #endif /* CONFIG_SOC_MIMXRT798S_CM33_CPU0 */
 
 	BOARD_InitAHBSC();
 
+#if defined(CONFIG_SECOND_CORE_MCUX)
+	POWER_DisablePD(kPDRUNCFG_SHUT_SENSEP_MAINCLK);
+	POWER_ApplyPD();
+#endif
+
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(edma0), okay)
 	CLOCK_EnableClock(kCLOCK_Dma0);
 	RESET_ClearPeripheralReset(kDMA0_RST_SHIFT_RSTn);
@@ -615,3 +625,45 @@ static void edma_enable_all_request(uint8_t instance)
 	}
 }
 #endif
+
+#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
+/**
+ * @brief Kickoff secondary core (CPU1).
+ *
+ * Kick the secondary core out of reset and wait for it to indicate boot. The
+ * core image was already copied to RAM in soc_early_init_hook()
+ *
+ * @return 0
+ */
+static int second_core_boot(void)
+{
+	/* Get the boot address for the second core */
+	uint32_t boot_address = (uint32_t)(DT_REG_ADDR(DT_NODELABEL(sram_code)));
+
+	PMC0->PDRUNCFG2 &= ~0x3FFC0000;
+	PMC0->PDRUNCFG3 &= ~0x3FFC0000;
+
+	/* RT700 specific CPU1 boot sequence */
+	/* Glikey write enable, GLIKEY4 */
+	GlikeyWriteEnable(GLIKEY4, 1U);
+
+	/* Boot source for Core 1 from RAM. */
+	SYSCON3->CPU1_NSVTOR = ((uint32_t)(void *)boot_address >> 7U);
+	SYSCON3->CPU1_SVTOR = ((uint32_t)(void *)boot_address >> 7U);
+
+	GlikeyClearConfig(GLIKEY4);
+
+	/* Enable cpu1 clock. */
+	CLOCK_EnableClock(kCLOCK_Cpu1);
+
+	/* Clear reset*/
+	RESET_ClearPeripheralReset(kCPU1_RST_SHIFT_RSTn);
+
+	/* Release cpu wait*/
+	SYSCON3->CPU_STATUS &= ~SYSCON3_CPU_STATUS_CPU_WAIT_MASK;
+
+	return 0;
+}
+
+SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif

boards/nxp/mimxrt700_evk/board.cmake

@@ -1,10 +1,10 @@
 #
-# Copyright 2024, 2025 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
-if(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
+if(CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SECOND_CORE_MCUX)
   board_runner_args(jlink "--device=MIMXRT798S_M33_0" "--reset-after-load")
   board_runner_args(linkserver  "--device=MIMXRT798S:MIMXRT700-EVK")
   board_runner_args(linkserver  "--override=/device/memory/4=")

boards/nxp/mimxrt700_evk/doc/index.rst

@@ -128,6 +128,18 @@ To build the hello_world sample for the i.MX RT700 HiFi 4 DSP core:
    :board: mimxrt700_evk/mimxrt798s/hifi4
    :goals: build
 
+Multicore Core Operation
+************************
+
+The MIMXRT700-EVK supports multicore core operation with all cores, the Cortex-M33 CPU0, Cortex-M33 CPU1,
+HiFi1 DSP and HiFi4 DSP.
+By default, the CM33 CPU0 core is the boot core and is responsible for initializing the system and
+starting the CM33 CPU1 core and/or HiFi4 DSP.
+The CM33 CPU1 is responsible to boot the HiFi1 DSP.
+
+Usually boot process is that core responsible for booting the secondary core(s) will copy its firmware/image
+to the designated memory location and then release the secondary core from reset.
+
 Programming and Debugging
 *************************
 

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts

@@ -336,6 +336,33 @@ zephyr_lcdif: &lcdif {};
 		jedec-id = [c2 81 3a];
 		erase-block-size = <DT_SIZE_K(4)>;
 		write-block-size = <2>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/*
+			 * Partition sizes must be aligned
+			 * to the flash memory sector size of 4KB.
+			 */
+			boot_partition: partition@0 {
+				label = "mcuboot";
+				reg = <0x00000000 DT_SIZE_K(128)>;
+			};
+			slot0_partition: partition@20000 {
+				label = "image-0";
+				reg = <0x00020000 DT_SIZE_M(7)>;
+			};
+			slot1_partition: partition@720000 {
+				label = "image-1";
+				reg = <0x00720000 DT_SIZE_M(7)>;
+			};
+			storage_partition: partition@E20000 {
+				label = "storage";
+				reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>;
+			};
+		};
 	};
 };
 
@@ -386,7 +413,11 @@ p3t1755dp_ard_i2c_interface: &flexcomm8_lpi2c8 {};
 	status = "okay";
 };
 
-&mbox4 {
+&mbox1_a {
+	status = "okay";
+};
+
+&mbox4_a {
 	status = "okay";
 };
 

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts

@@ -24,7 +24,7 @@
 
 	chosen {
 		zephyr,flash = &sram_code;
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram3;
 		zephyr,console = &flexcomm19_lpuart19;
 		zephyr,shell-uart = &flexcomm19_lpuart19;
 	};
@@ -110,3 +110,7 @@
 &rtc1 {
 	status = "okay";
 };
+
+&mbox1_b {
+	status = "okay";
+};

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts

@@ -73,6 +73,6 @@
 	mclk-output;
 };
 
-&mbox4 {
+&mbox4_b {
 	status = "okay";
 };