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Fix some RISC-V ABI issues and add ILP32/LP64 (soft float) to module tests #21610

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merged 5 commits into from
Oct 17, 2024

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alexrp
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@alexrp alexrp commented Oct 6, 2024

Note that I'm not adding ILP32F/LP64F (hard f32, soft f64) to the test matrix. They work, but they're used extremely rarely, so I don't think it's worth wasting valuable CI resources on them. For perspective, glibc doesn't support them, and musl needs a patch for them to work, so I doubt anyone cares much.

@alexrp alexrp requested a review from andrewrk October 6, 2024 10:32
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alexrp commented Oct 6, 2024

cc @Rexicon226

.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv32-linux-none",
.cpu_features = "baseline-d-f",
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(The plan is for this to become a proper ABI in std.Target with #20690.)

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All the changes make sense to me on the RISC-V side of things.

test/tests.zig Outdated Show resolved Hide resolved
@andrewrk andrewrk merged commit 8504e1f into ziglang:master Oct 17, 2024
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Great!

@alexrp alexrp deleted the riscv-abis branch October 17, 2024 21:13
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4 participants